SPR: Release v1.15 event files

This commit releases SPR v1.15 events and updates mapfile.csv accordingly.
intel · Jul 17, 2023 · 76dfb81 · 76dfb81
1 parent 44fe368
commit 76dfb81
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Showing 4 changed files with 61 additions and 13 deletions.
diff --git a/SPR/events/sapphirerapids_core.json b/SPR/events/sapphirerapids_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [
@@ -8311,6 +8311,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0x2A,0x2B",
+      "UMask": "0x01",
+      "EventName": "OCR.DEMAND_DATA_RD.PMM",
+      "BriefDescription": "Counts demand data reads that were supplied by PMM.",
+      "PublicDescription": "Counts demand data reads that were supplied by PMM.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x1a6,0x1a7",
+      "MSRValue": "0x703C00001",
+      "CollectPEBSRecord": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "1",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0x2A,0x2B",
       "UMask": "0x01",
@@ -8911,6 +8935,30 @@
       "Deprecated": "0",
       "Speculative": "0"
     },
+    {
+      "EventCode": "0x2A,0x2B",
+      "UMask": "0x01",
+      "EventName": "OCR.DEMAND_DATA_RD.LOCAL_SOCKET_PMM",
+      "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
+      "PublicDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0",
+      "SampleAfterValue": "100003",
+      "MSRIndex": "0x1a6,0x1a7",
+      "MSRValue": "0x700C00001",
+      "CollectPEBSRecord": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "1",
+      "Deprecated": "0",
+      "Speculative": "0"
+    },
     {
       "EventCode": "0x2A,0x2B",
       "UMask": "0x01",

diff --git a/SPR/events/sapphirerapids_uncore.json b/SPR/events/sapphirerapids_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [

diff --git a/SPR/events/sapphirerapids_uncore_experimental.json b/SPR/events/sapphirerapids_uncore_experimental.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.14",
-    "DatePublished": "06/19/2023",
-    "Version": "1.14",
+    "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.15",
+    "DatePublished": "06/28/2023",
+    "Version": "1.15",
     "Legend": ""
   },
   "Events": [

diff --git a/mapfile.csv b/mapfile.csv
@@ -115,10 +115,10 @@ GenuineIntel-6-8C,V1.13,/TGL/events/tigerlake_uncore.json,uncore,,,
 GenuineIntel-6-8D,V1.13,/TGL/events/tigerlake_uncore.json,uncore,,,
 GenuineIntel-6-8C,V1.13,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-8D,V1.13,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_core.json,core,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore.json,uncore,,,
-GenuineIntel-6-8F,V1.14,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-CF,V1.14,/SPR/events/sapphirerapids_core.json,core,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_core.json,core,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_uncore.json,uncore,,,
+GenuineIntel-6-8F,V1.15,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-CF,V1.15,/SPR/events/sapphirerapids_core.json,core,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_core.json,core,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore.json,uncore,,,
 GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,