Make VLEN and ELEN configurable and remove registers

Remove the registers which don't exist in the ISA and were unnecessary. They have been replaced by sys_ callbacks which are not currently connected to CLI arguments, but we can hook them up to the new config system when it is available.

Co-authored-by: Yui5427 <785369607@qq.com>

c_emulator/riscv_platform.c

@@ -82,6 +82,16 @@ uint64_t sys_pmp_grain(unit u)
   return rv_pmp_grain;
 }
 
+uint64_t sys_vector_vlen_exp(unit)
+{
+  return rv_vector_vlen_exp;
+}
+
+uint64_t sys_vector_elen_exp(unit)
+{
+  return rv_vector_elen_exp;
+}
+
 bool sys_enable_writable_misa(unit u)
 {
   return rv_enable_writable_misa;

c_emulator/riscv_platform.h

@@ -17,6 +17,9 @@ bool sys_enable_zicboz(unit);
 uint64_t sys_pmp_count(unit);
 uint64_t sys_pmp_grain(unit);
 
+uint64_t sys_vector_vlen_exp(unit);
+uint64_t sys_vector_elen_exp(unit);
+
 bool plat_enable_dirty_update(unit);
 bool plat_enable_misaligned_access(unit);
 bool plat_mtval_has_illegal_inst_bits(unit);

c_emulator/riscv_platform_impl.c

@@ -6,6 +6,9 @@
 uint64_t rv_pmp_count = 0;
 uint64_t rv_pmp_grain = 0;
 
+uint64_t rv_vector_vlen_exp = 0x9;
+uint64_t rv_vector_elen_exp = 0x6;
+
 bool rv_enable_svinval = false;
 bool rv_enable_zcb = false;
 bool rv_enable_zfinx = false;

c_emulator/riscv_platform_impl.h

@@ -11,6 +11,9 @@
 extern uint64_t rv_pmp_count;
 extern uint64_t rv_pmp_grain;
 
+extern uint64_t rv_vector_vlen_exp;
+extern uint64_t rv_vector_elen_exp;
+
 extern bool rv_enable_svinval;
 extern bool rv_enable_zcb;
 extern bool rv_enable_zfinx;

model/riscv_sys_control.sail

@@ -470,8 +470,6 @@ function init_sys() -> unit = {
   menvcfg.bits = zeros();
   senvcfg.bits = zeros();
   /* initialize vector csrs */
-  elen               = 0b1; /* ELEN=64 as the common case */
-  vlen               = 0b0100; /* VLEN=512 as a default value */
   vlenb              = to_bits(xlen, 2 ^ (get_vlen_pow() - 3)); /* vlenb holds the constant value VLEN/8 */
   /* VLEN value needs to be manually changed currently.
    * See riscv_vlen.sail for details.

model/riscv_vlen.sail

@@ -6,48 +6,17 @@
 /*  SPDX-License-Identifier: BSD-2-Clause                                                */
 /*=======================================================================================*/
 
-register elen : bits(1)
+val sys_vector_elen_exp = pure "sys_vector_elen_exp" : unit -> range(3, 16)
 
-val get_elen_pow : unit -> {5, 6}
+function get_elen_pow() -> range(3, 16) = sys_vector_elen_exp()
 
-function get_elen_pow() = match elen {
-    0b0 => 5,
-    0b1 => 6
-}
 /* Note: ELEN=32 requires a different encoding of the CSR vtype.
  * The current version of vtype implementation corresponds to the ELEN=64 configuration.
  * TODO: the configurarion of ELEN and its corresponding vtype implementations.
  */
 
-register vlen : bits(4)
+val sys_vector_vlen_exp = pure "sys_vector_vlen_exp" : unit -> range(3, 16)
 
-val get_vlen_pow : unit -> {5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}
-
-function get_vlen_pow() = match vlen {
-    0b0000 => 5,
-    0b0001 => 6,
-    0b0010 => 7,
-    0b0011 => 8,
-    0b0100 => 9,
-    0b0101 => 10,
-    0b0110 => 11,
-    0b0111 => 12,
-    0b1000 => 13,
-    0b1001 => 14,
-    0b1010 => 15,
-    _      => 16
-}
+function get_vlen_pow() -> range(3, 16) = sys_vector_vlen_exp()
 
 type vlenmax : Int = 65536
-
-/* Note: At present, the values of elen and vlen need to be manually speficied
- * in the init_sys() function of riscv_sys_control.sail before compiling the emulators,
- * e.g.,
- *  vlen = 0b0101;
- *  elen = 0b1;
- * means VLEN = 1024 and ELEN = 64,
- * They will be configurable when user-specified configuration is supported in Sail.
- *
- * Also, VLEN >= ELEN must be satisfied and this condition check should be added
- * after their initialization.
- */