RVcore VLSI Chip Project

RISC-V is a RISC-based open instruction set architecture. The basic 32-bit integer instruction set in RISC-V is defined as RV32I. We are developing an optimized RV32I processor named RVCoreP, adopting five-stage pipelining targetting both FPGAs and ASICs. This project aims to evaluate our preliminary processor design regarding operating frequency and power consumption.