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[VPlan] Request lane 0 for pointer arg in PtrAdd.
After 7f74651, the pointer operand may be replicated of a PtrAdd. Instead of requesting a single scalar, request lane 0, which correctly handles the case when there is a scalar-per-lane. Fixes llvm#111606.
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llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 | ||
; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s | ||
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" | ||
target triple = "x86_64-unknown-linux-gnu" | ||
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; Test for https://github.com/llvm/llvm-project/issues/111606. | ||
define ptr @test_interleave_ptradd_with_replicated_op(ptr %m) #0 { | ||
; CHECK-LABEL: define ptr @test_interleave_ptradd_with_replicated_op( | ||
; CHECK-SAME: ptr [[M:%.*]]) #[[ATTR0:[0-9]+]] { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | ||
; CHECK: [[VECTOR_PH]]: | ||
; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[M]], i64 768 | ||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | ||
; CHECK: [[VECTOR_BODY]]: | ||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | ||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8 | ||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 | ||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 8 | ||
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 16 | ||
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 24 | ||
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 32 | ||
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 40 | ||
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 48 | ||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 56 | ||
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 64 | ||
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 72 | ||
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 80 | ||
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 88 | ||
; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 96 | ||
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 104 | ||
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 112 | ||
; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 120 | ||
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP0]] | ||
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP1]] | ||
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP2]] | ||
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP3]] | ||
; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP4]] | ||
; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP5]] | ||
; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP6]] | ||
; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP7]] | ||
; CHECK-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP8]] | ||
; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP9]] | ||
; CHECK-NEXT: [[NEXT_GEP11:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP10]] | ||
; CHECK-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP11]] | ||
; CHECK-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP12]] | ||
; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP13]] | ||
; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP14]] | ||
; CHECK-NEXT: [[NEXT_GEP16:%.*]] = getelementptr i8, ptr [[M]], i64 [[TMP15]] | ||
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 4 | ||
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 4 | ||
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[NEXT_GEP3]], i64 4 | ||
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[NEXT_GEP4]], i64 4 | ||
; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[NEXT_GEP5]], i64 4 | ||
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[NEXT_GEP6]], i64 4 | ||
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[NEXT_GEP7]], i64 4 | ||
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[NEXT_GEP8]], i64 4 | ||
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[NEXT_GEP9]], i64 4 | ||
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[NEXT_GEP10]], i64 4 | ||
; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[NEXT_GEP11]], i64 4 | ||
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[NEXT_GEP12]], i64 4 | ||
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[NEXT_GEP13]], i64 4 | ||
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[NEXT_GEP14]], i64 4 | ||
; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[NEXT_GEP15]], i64 4 | ||
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[NEXT_GEP16]], i64 4 | ||
; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP16]], i32 -4 | ||
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP20]], i32 -4 | ||
; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP24]], i32 -4 | ||
; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[TMP28]], i32 -4 | ||
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, ptr [[TMP32]], align 4 | ||
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> | ||
; CHECK-NEXT: [[STRIDED_VEC17:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> | ||
; CHECK-NEXT: [[WIDE_VEC18:%.*]] = load <8 x i32>, ptr [[TMP33]], align 4 | ||
; CHECK-NEXT: [[STRIDED_VEC19:%.*]] = shufflevector <8 x i32> [[WIDE_VEC18]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> | ||
; CHECK-NEXT: [[STRIDED_VEC20:%.*]] = shufflevector <8 x i32> [[WIDE_VEC18]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> | ||
; CHECK-NEXT: [[WIDE_VEC21:%.*]] = load <8 x i32>, ptr [[TMP34]], align 4 | ||
; CHECK-NEXT: [[STRIDED_VEC22:%.*]] = shufflevector <8 x i32> [[WIDE_VEC21]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> | ||
; CHECK-NEXT: [[STRIDED_VEC23:%.*]] = shufflevector <8 x i32> [[WIDE_VEC21]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> | ||
; CHECK-NEXT: [[WIDE_VEC24:%.*]] = load <8 x i32>, ptr [[TMP35]], align 4 | ||
; CHECK-NEXT: [[STRIDED_VEC25:%.*]] = shufflevector <8 x i32> [[WIDE_VEC24]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> | ||
; CHECK-NEXT: [[STRIDED_VEC26:%.*]] = shufflevector <8 x i32> [[WIDE_VEC24]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> | ||
; CHECK-NEXT: [[TMP36:%.*]] = add <4 x i32> [[STRIDED_VEC17]], [[STRIDED_VEC]] | ||
; CHECK-NEXT: [[TMP37:%.*]] = add <4 x i32> [[STRIDED_VEC20]], [[STRIDED_VEC19]] | ||
; CHECK-NEXT: [[TMP38:%.*]] = add <4 x i32> [[STRIDED_VEC23]], [[STRIDED_VEC22]] | ||
; CHECK-NEXT: [[TMP39:%.*]] = add <4 x i32> [[STRIDED_VEC26]], [[STRIDED_VEC25]] | ||
; CHECK-NEXT: [[TMP40:%.*]] = extractelement <4 x i32> [[TMP36]], i32 0 | ||
; CHECK-NEXT: store i32 [[TMP40]], ptr [[NEXT_GEP]], align 4 | ||
; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i32> [[TMP36]], i32 1 | ||
; CHECK-NEXT: store i32 [[TMP41]], ptr [[NEXT_GEP2]], align 4 | ||
; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[TMP36]], i32 2 | ||
; CHECK-NEXT: store i32 [[TMP42]], ptr [[NEXT_GEP3]], align 4 | ||
; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[TMP36]], i32 3 | ||
; CHECK-NEXT: store i32 [[TMP43]], ptr [[NEXT_GEP4]], align 4 | ||
; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[TMP37]], i32 0 | ||
; CHECK-NEXT: store i32 [[TMP44]], ptr [[NEXT_GEP5]], align 4 | ||
; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP37]], i32 1 | ||
; CHECK-NEXT: store i32 [[TMP45]], ptr [[NEXT_GEP6]], align 4 | ||
; CHECK-NEXT: [[TMP46:%.*]] = extractelement <4 x i32> [[TMP37]], i32 2 | ||
; CHECK-NEXT: store i32 [[TMP46]], ptr [[NEXT_GEP7]], align 4 | ||
; CHECK-NEXT: [[TMP47:%.*]] = extractelement <4 x i32> [[TMP37]], i32 3 | ||
; CHECK-NEXT: store i32 [[TMP47]], ptr [[NEXT_GEP8]], align 4 | ||
; CHECK-NEXT: [[TMP48:%.*]] = extractelement <4 x i32> [[TMP38]], i32 0 | ||
; CHECK-NEXT: store i32 [[TMP48]], ptr [[NEXT_GEP9]], align 4 | ||
; CHECK-NEXT: [[TMP49:%.*]] = extractelement <4 x i32> [[TMP38]], i32 1 | ||
; CHECK-NEXT: store i32 [[TMP49]], ptr [[NEXT_GEP10]], align 4 | ||
; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[TMP38]], i32 2 | ||
; CHECK-NEXT: store i32 [[TMP50]], ptr [[NEXT_GEP11]], align 4 | ||
; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP38]], i32 3 | ||
; CHECK-NEXT: store i32 [[TMP51]], ptr [[NEXT_GEP12]], align 4 | ||
; CHECK-NEXT: [[TMP52:%.*]] = extractelement <4 x i32> [[TMP39]], i32 0 | ||
; CHECK-NEXT: store i32 [[TMP52]], ptr [[NEXT_GEP13]], align 4 | ||
; CHECK-NEXT: [[TMP53:%.*]] = extractelement <4 x i32> [[TMP39]], i32 1 | ||
; CHECK-NEXT: store i32 [[TMP53]], ptr [[NEXT_GEP14]], align 4 | ||
; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[TMP39]], i32 2 | ||
; CHECK-NEXT: store i32 [[TMP54]], ptr [[NEXT_GEP15]], align 4 | ||
; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x i32> [[TMP39]], i32 3 | ||
; CHECK-NEXT: store i32 [[TMP55]], ptr [[NEXT_GEP16]], align 4 | ||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | ||
; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 | ||
; CHECK-NEXT: br i1 [[TMP56]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | ||
; CHECK: [[MIDDLE_BLOCK]]: | ||
; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]] | ||
; CHECK: [[SCALAR_PH]]: | ||
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[M]], %[[ENTRY]] ] | ||
; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 97, %[[MIDDLE_BLOCK]] ], [ 1, %[[ENTRY]] ] | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ] | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | ||
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 8 | ||
; CHECK-NEXT: [[P_4:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 4 | ||
; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[P_4]], align 4 | ||
; CHECK-NEXT: [[P_0:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 0 | ||
; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[P_0]], align 4 | ||
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[L_1]], [[L_2]] | ||
; CHECK-NEXT: store i32 [[ADD]], ptr [[PTR_IV]], align 4 | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV]], 100 | ||
; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[P_4_LCSSA:%.*]] = phi ptr [ [[P_4]], %[[LOOP]] ], [ [[TMP31]], %[[MIDDLE_BLOCK]] ] | ||
; CHECK-NEXT: ret ptr [[P_4_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
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loop: ; preds = %loop, %entry | ||
%ptr.iv = phi ptr [ %m, %entry ], [ %ptr.iv.next, %loop ] | ||
%iv = phi i32 [ 1, %entry ], [ %iv.next, %loop ] | ||
%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 8 | ||
%p.4 = getelementptr i8, ptr %ptr.iv, i64 4 | ||
%l.1 = load i32, ptr %p.4, align 4 | ||
%p.0 = getelementptr i8, ptr %ptr.iv, i64 0 | ||
%l.2 = load i32, ptr %p.0, align 4 | ||
%add = add i32 %l.1, %l.2 | ||
store i32 %add, ptr %ptr.iv, align 4 | ||
%iv.next = add i32 %iv, 1 | ||
%tobool.not = icmp eq i32 %iv, 100 | ||
br i1 %tobool.not, label %exit, label %loop | ||
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exit: ; preds = %loop | ||
ret ptr %p.4 | ||
} | ||
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attributes #0 = { "target-cpu"="znver2" } | ||
;. | ||
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} | ||
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} | ||
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} | ||
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} | ||
;. |