This is my notes and code for a 6502 breadboard computer built from Ben Eater's 6502 kit.
| Id | Part number | Description | Comments |
|---|---|---|---|
| U1 | WDC65C02S | 6502 Microprocessor, CMOS | |
| U2 | AT28C265 | 32K x 8 EEPROM | |
| U3 | HM65256B | 32K x 8 Static RAM | |
| U4 | W65C22 | Versatile Interface Adapter (VIA) | |
| U5 | 74HC00 | Quad 2-Input NAND gate | |
| X1 | OSC1 | 1 MHz clock oscillator |
| Address (hex) | Region | Device | Comments | |
|---|---|---|---|---|
| $0000 | $3fff | RAM | 62256 SRAM | Only 16K used out of 32K available. |
| $4000 | $5fff | - | - | Reserved for future use. |
| $6000 | $7fff | I/O | 65C22 VIA | 16 Registers, 2 8-bit I/O ports |
| $8000 | $ffff | ROM | AT28C256 EEPROM | 32K x 8 EEPROM |
Address Decoding Logic
See Garth Wilson's address decoding document to learn about 6502 address decoding design.
The BE6502 design prioritizes simplicity over functionality. The address decoding is implemented using a single quad-NAND gate. However, the trade off for this simplicity is lack of efficiency. Only 16K of RAM is accessible, even though the HM65256B provides 32K, and 2k of the memory map is allocated for I/O, but the 65C22 VIA has only 16 addressable registers.
The full 32K of the ROM is available, which is probably far more than is needed for this computer. The ROM is located on the bottom half of the memory map so the reset vector is available in ROM on power up.
A more sophisticated address decoding scheme would make better use of the resources, but at a cost of increased complexity and chip count.
The following describes the BE6502 decoding logic:
The ROM is selected when ROM /CS is low. The ROM /CS pin is set low when the A15 address line is high, so the ROM is selected in the 32K address range $8000 to $ffff.
The RAM is selected when the RAM /CS and /OE are both low. The RAM /CS pin is set low when the A15 address line is low, and the RAM /OE pin is set low when the A14 address line is low, so the RAM is selected in the 16k address range $0000 to $3fff. In addition, the RAM /CS is tied to the clock signal to ensure the address and data lines are quiescent before the RAM is selected. This helps to prevent writing garbage to RAM memory. The RAM /CS will be set low only when A15 is low and the clock is high.
The VIA is selected when the VIA CS1 is high and VIA /CS2 is low. The CS1 pin is set to high when the A13 line is high and the /CS2 pin is set to low when the A15 line is low and the A14 line is high, so the VIA is selected in when the address lines are set to any address in the range of $6000 to $7fff (8k).
The following logic table shows the address decoding logic combinations.
| Address pins | Clock | ROM | RAM | VIA | Selected | ||||
|---|---|---|---|---|---|---|---|---|---|
| A15 | A14 | A13 | CLK | /CS | /CS | /OE | CS1 | /CS2 | |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | RAM |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | RAM |
| 0 | 1 | 0 | x | 1 | 0 | 1 | 0 | 0 | Not used |
| 0 | 1 | 1 | x | 1 | 0 | 1 | 1 | 0 | VIA |
| 1 | 0 | 0 | x | 0 | 1 | 0 | 0 | 1 | ROM |
| 1 | 0 | 1 | x | 0 | 1 | 0 | 1 | 1 | ROM |
| 1 | 1 | 0 | x | 0 | 1 | 0 | 0 | 1 | ROM |
| 1 | 1 | 1 | x | 0 | 1 | 0 | 1 | 1 | ROM |
The 65C22 VIA is enabled when the address lines are the range $6000 to $7fff, however only the bottom four address lines (A0 to A3) are connected to the register selection pins. The registers could be selected when the address bits are in that range, but as a convention the registers are only accessed when in the address range $6000 to $600E.
| $6000 | ORB/IRB Output Register "B" Input Register "B" |
| $6001 | ORA/IRA Output Register "A" Input Register "A" |
| $6002 | DDRB Data Direction Register "B" |
| $6003 | DDRA Data Direction Register "A" |
| $6004 - $600b | Not used |
| $600c | PCR Peripheral Control Register |
| $600d | IFR Interrupt Flag Register |
| $600e | IER Interrupt Enable Register |
| $600f | Not used. |
| $6010 - $7fff | Reserved. |