Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
build		build
toolchain		toolchain
verilog		verilog
xilinx		xilinx
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
go		go
sim_main.cpp		sim_main.cpp

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j1

The J1 CPU

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The J1 CPU

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Forth 43.3%
Verilog 31.8%
Makefile 14.8%
Python 6.4%
C++ 3.6%
C 0.1%