Update cachesim.

Add Policy FIFO for cache replacement.

src/cachesim/cachesim.cpp

@@ -115,13 +115,19 @@ CacheSim::locateEvictionWay(const CacheTransaction &transaction) {
   std::pair<unsigned, CacheSim::CacheWay *> ew;
   ew.first = s_invalidIndex;
   ew.second = nullptr;
-
   // Locate a new way based on replacement policy.
   if (m_replPolicy == ReplPolicy::Random) {
     // Select a random way
     ew.first = std::rand() % getWays();
     ew.second = &cacheLine[ew.first];
-  } else if (m_replPolicy == ReplPolicy::LRU) {
+  } 
+    else if (m_replPolicy == ReplPolicy::FIFO){
+        ew.first = CacheSim::counter;
+        ew.second = &cacheLine[ew.first];
+        CacheSim::counter += 1;
+	CacheSim::counter %= getWays();
+   }
+    else if (m_replPolicy == ReplPolicy::LRU) {
     if (getWays() == 1) {
       // Nothing to do if we are in LRU and only have 1 set.
       ew.first = 0;

src/cachesim/cachesim.h

@@ -16,7 +16,7 @@ class CacheSim;
 
 enum WriteAllocPolicy { WriteAllocate, NoWriteAllocate };
 enum WritePolicy { WriteThrough, WriteBack };
-enum ReplPolicy { Random, LRU };
+enum ReplPolicy { Random, LRU, FIFO};
 
 struct CachePreset {
   QString name;
@@ -91,7 +91,7 @@ class CacheSim : public CacheInterface {
   Q_OBJECT
 public:
   static constexpr unsigned s_invalidIndex = static_cast<unsigned>(-1);
-
+  int counter = 0;
   struct CacheSize {
     unsigned bits = 0;
     std::vector<QString> components;
@@ -329,7 +329,7 @@ public slots:
 };
 
 const static std::map<ReplPolicy, QString> s_cacheReplPolicyStrings{
-    {ReplPolicy::Random, "Random"}, {ReplPolicy::LRU, "LRU"}};
+    {ReplPolicy::Random, "Random"}, {ReplPolicy::LRU, "LRU"}, {ReplPolicy::FIFO, "FIFO"}};
 const static std::map<WriteAllocPolicy, QString> s_cacheWriteAllocateStrings{
     {WriteAllocPolicy::WriteAllocate, "Write allocate"},
     {WriteAllocPolicy::NoWriteAllocate, "No write allocate"}};