Skip to content

[ARM] Restore cache information #292

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
chaitu236 wants to merge 2 commits into
base: nilrt/master/6.18
Choose a base branch
from
Open

[ARM] Restore cache information #292

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
44bbfba
ARM: dts: zynq: Describe CPU cache hierarchy
chaitu236 Aug 29, 2026
ada8970
cacheinfo: Preserve legacy cache size format for NI ARM
chaitu236 Aug 29, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 17 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-7000.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,13 @@
clocks = <&clkc 3>;
clock-latency = <1000>;
cpu0-supply = <&regulator_vccpint>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
d-cache-sets = <256>;
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
666667 1000000
Expand All @@ -38,6 +45,13 @@
device_type = "cpu";
reg = <1>;
clocks = <&clkc 3>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
d-cache-sets = <256>;
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <256>;
next-level-cache = <&L2>;
};
};

Expand Down Expand Up @@ -191,6 +205,9 @@
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <32>;
cache-sets = <2048>;
};

mc: memory-controller@f8006000 {
Expand Down
1 change: 1 addition & 0 deletions arch/arm/configs/nati_zynq_defconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ CONFIG_PERF_EVENTS=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_ZYNQ=y
CONFIG_NI_ZYNQ_GIC_LEGACY_IRQDOMAIN=y
CONFIG_NI_LEGACY_ARM_CACHEINFO_SIZE=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
Expand Down
9 changes: 9 additions & 0 deletions arch/arm/mach-zynq/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,3 +25,12 @@ config NI_ZYNQ_GIC_LEGACY_IRQDOMAIN
This preserves compatibility with NI drivers that use fixed IRQs.
Enable this only on NI Zynq systems that require the legacy IRQ
numbering contract.

config NI_LEGACY_ARM_CACHEINFO_SIZE
bool "Use legacy cache size units on NI ARM targets"
depends on ARCH_ZYNQ
help
Report CPU cache sizes in bytes through sysfs instead of using the
generic cacheinfo K suffix. This preserves compatibility with released
NI ARM software that expects the legacy NI kernel representation.
Enable this only for systems that require this compatibility behavior.
3 changes: 3 additions & 0 deletions drivers/base/cacheinfo.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -664,6 +664,9 @@ static ssize_t size_show(struct device *dev,
{
struct cacheinfo *this_leaf = dev_get_drvdata(dev);

if (IS_ENABLED(CONFIG_NI_LEGACY_ARM_CACHEINFO_SIZE))
return sysfs_emit(buf, "%u\n", this_leaf->size);

return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10);
}

Expand Down
Loading