Aligning documentation to the new folder structure.

Including the new AscEditor class on the description

PyLTSpice/sim/sim_analysis.py → PyLTSpice/sim/tookit/failure_modes.py

@@ -9,49 +9,22 @@
 #   |_|    \__, |_____|_| |____/| .__/|_|\___\___|
 #          |___/                |_|
 #
-# Name:        sim_analysis.py
-# Purpose:     Classes to automate Monte-Carlo, FMEA or Worst Case Analysis
-#              be updated by user instructions
+# Name:        failure_modes.py
+# Purpose:     Class to automate FMEA
 #
 # Author:      Nuno Brum (nuno.brum@gmail.com)
 #
-# Created:     23-12-2016
+# Created:     10-08-2023
 # Licence:     refer to the LICENSE file
 # -------------------------------------------------------------------------------
 
 from collections import OrderedDict
-from typing import Iterable, Union, Optional
+from typing import Union, Optional, Iterable
 
-from .sim_runner import AnyRunner
-from ..editor.base_editor import BaseEditor, ComponentNotFoundError
-from ..sim.simulator import Simulator
-
-
-class SimAnalysis(object):
-    """
-    Base class for making Monte-Carlo, Extreme Value Analysis (EVA) or Failure Mode and Effects Analysis.
-    As a base class, a certain number of assertions must be made on the simulation results that will make the pass/fail.
-
-    Note: For the time being only measurements done with .MEAS are possible. At a later stage the parsing of RAW files
-    will be possible, although, it seems that the later solution is less computing intense.
-    """
-
-    def __init__(self, circuit_file: Union[str, BaseEditor], simulator: Optional[Simulator] = None,
-                 runner: Optional[AnyRunner] = None):
-        if isinstance(circuit_file, str):
-            from ..editor.spice_editor import SpiceEditor
-            self.editor = SpiceEditor(circuit_file)
-        else:
-            self.editor = circuit_file
-        if simulator is None:
-            from ..sim.ltspice_simulator import LTspice
-            self.simulator = LTspice()
-        else:
-            self.simulator = simulator
-        if runner is None:
-            from ..sim.sim_runner import SimRunner
-            self.runner = SimRunner(parallel_sims=1, timeout=None, verbose=False, output_folder=None)
-        self.simulations = OrderedDict()
+from editor.base_editor import BaseEditor, ComponentNotFoundError
+from .sim_analysis import SimAnalysis
+from sim.sim_runner import AnyRunner
+from sim.simulator import Simulator
 
 
 class FailureMode(SimAnalysis):

PyLTSpice/sim/tookit/montecarlo.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python
+# coding=utf-8
+
+# -------------------------------------------------------------------------------
+#    ____        _   _____ ____        _
+#   |  _ \ _   _| | |_   _/ ___| _ __ (_) ___ ___
+#   | |_) | | | | |   | | \___ \| '_ \| |/ __/ _ \
+#   |  __/| |_| | |___| |  ___) | |_) | | (_|  __/
+#   |_|    \__, |_____|_| |____/| .__/|_|\___\___|
+#          |___/                |_|
+#
+# Name:        montecarlo.py
+# Purpose:     Classes to automate Monte-Carlo simulations
+#
+# Author:      Nuno Brum (nuno.brum@gmail.com)
+#
+# Created:     10-08-2023
+# Licence:     refer to the LICENSE file
+# -------------------------------------------------------------------------------

PyLTSpice/sim/tookit/sim_analysis.py

@@ -0,0 +1,56 @@
+#!/usr/bin/env python
+# coding=utf-8
+
+# -------------------------------------------------------------------------------
+#    ____        _   _____ ____        _
+#   |  _ \ _   _| | |_   _/ ___| _ __ (_) ___ ___
+#   | |_) | | | | |   | | \___ \| '_ \| |/ __/ _ \
+#   |  __/| |_| | |___| |  ___) | |_) | | (_|  __/
+#   |_|    \__, |_____|_| |____/| .__/|_|\___\___|
+#          |___/                |_|
+#
+# Name:        sim_analysis.py
+# Purpose:     Classes to automate Monte-Carlo, FMEA or Worst Case Analysis
+#              be updated by user instructions
+#
+# Author:      Nuno Brum (nuno.brum@gmail.com)
+#
+# Created:     06-07-2021
+# Licence:     refer to the LICENSE file
+# -------------------------------------------------------------------------------
+
+from collections import OrderedDict
+from typing import Union, Optional
+
+from ...sim.sim_runner import AnyRunner
+from ...editor.base_editor import BaseEditor
+from ...sim.simulator import Simulator
+
+
+class SimAnalysis(object):
+    """
+    Base class for making Monte-Carlo, Extreme Value Analysis (EVA) or Failure Mode and Effects Analysis.
+    As a base class, a certain number of assertions must be made on the simulation results that will make the pass/fail.
+
+    Note: For the time being only measurements done with .MEAS are possible. At a later stage the parsing of RAW files
+    will be possible, although, it seems that the later solution is less computing intense.
+    """
+
+    def __init__(self, circuit_file: Union[str, BaseEditor], simulator: Optional[Simulator] = None,
+                 runner: Optional[AnyRunner] = None):
+        if isinstance(circuit_file, str):
+            from ..editor.spice_editor import SpiceEditor
+            self.editor = SpiceEditor(circuit_file)
+        else:
+            self.editor = circuit_file
+        if simulator is None:
+            from ..sim.ltspice_simulator import LTspice
+            self.simulator = LTspice()
+        else:
+            self.simulator = simulator
+        if runner is None:
+            from ..sim.sim_runner import SimRunner
+            self.runner = SimRunner(parallel_sims=1, timeout=None, verbose=False, output_folder=None)
+        self.simulations = OrderedDict()
+
+

doc/classes/asc_editor.rst

@@ -0,0 +1,9 @@
+AscEditor
+============
+
+Class used for manipulating LTSpice asc files.
+
+.. autoclass:: PyLTSpice.editor.asc_editor.AscEditor
+   :members:
+   :undoc-members:
+   :show-inheritance:

doc/classes/editor_classes.rst

@@ -0,0 +1,9 @@
+Editor Classes
+==============
+
+.. toctree::
+   :maxdepth: 4
+
+   spice_editor
+   spice_circuit
+   asc_editor

doc/classes/raw_classes.rst

@@ -0,0 +1,13 @@
+========================
+Raw and Log File Classes
+========================
+
+.. toctree::
+   :maxdepth: 4
+
+   raw_read
+   trace
+   logreader
+   raw_write
+   write_trace
+

doc/classes/sim_client.rst

@@ -1,5 +1,6 @@
-SimClient (Under development)
-=============================
+=========
+SimClient
+=========
 
 .. autoclass:: PyLTSpice.client_server.sim_client.SimClient
    :members:

doc/classes/sim_server.rst

@@ -1,5 +1,6 @@
-SimServer (Under development)
-=============================
+=========
+SimServer
+=========
 
 .. autoclass:: PyLTSpice.client_server.sim_server.SimServer
    :members:

doc/classes/classes.rst → doc/classes/simulation_classes.rst

@@ -1,16 +1,11 @@
-==============
-Python Classes
-==============
-
+==================
+Simulation Classes
+==================
 .. toctree::
    :maxdepth: 4
-
-   spice_editor
-   spice_circuit
+
    sim_runner
    sim_simulator
-   raw_read
-   raw_write
    sim_client
    sim_server
 

doc/classes/spice_circuit.rst

@@ -1,7 +1,7 @@
 SpiceCircuit
 ============
 
-.. autoclass:: PyLTSpice.sim.spice_editor.SpiceCircuit
+.. autoclass:: PyLTSpice.editor.spice_editor.SpiceCircuit
    :members:
    :undoc-members:
    :show-inheritance:

doc/classes/spice_editor.rst

@@ -3,7 +3,7 @@ SpiceEditor
 
 Class used for manipulating SPICE netlists. Inherits from SpiceCircuit.
 
-.. autoclass:: PyLTSpice.sim.spice_editor.SpiceEditor
+.. autoclass:: PyLTSpice.editor.spice_editor.SpiceEditor
    :members:
    :undoc-members:
    :show-inheritance:

doc/classes/trace.rst

@@ -1,7 +1,12 @@
 RawRead Trace
 =============
 
-.. autoclass:: PyLTSpice.raw_classes.Trace
+.. autoclass:: PyLTSpice.raw.raw_classes.Axis
+   :members:
+   :undoc-members:
+   :show-inheritance:
+
+.. autoclass:: PyLTSpice.raw.raw_classes.TraceRead
    :members:
    :undoc-members:
    :show-inheritance:

doc/classes/write_trace.rst

@@ -1,7 +1,7 @@
 RawWrite Trace
 ==============
 
-.. autoclass:: PyLTSpice.raw_write.Trace
+.. autoclass:: PyLTSpice.raw.raw_write.Trace
    :members:
    :undoc-members:
    :show-inheritance: