Move assertion statement outside of always_comb block
#1467
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2 warnings
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format:
core/cache_subsystem/tag_cmp.sv#L88
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/cache_subsystem/tag_cmp.sv:88:- // assert that cache only hits on one way
core/cache_subsystem/tag_cmp.sv:89:- // this only needs to be checked one cycle after all ways have been requested
core/cache_subsystem/tag_cmp.sv:90:- onehot :
core/cache_subsystem/tag_cmp.sv:91:- assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
core/cache_subsystem/tag_cmp.sv:92:- else begin
core/cache_subsystem/tag_cmp.sv:93:- $fatal(1, "Hit should be one-hot encoded");
core/cache_subsystem/tag_cmp.sv:94:- end
core/cache_subsystem/tag_cmp.sv:88:+ // assert that cache only hits on one way
core/cache_subsystem/tag_cmp.sv:89:+ // this only needs to be checked one cycle after all ways have been requested
core/cache_subsystem/tag_cmp.sv:90:+ onehot :
core/cache_subsystem/tag_cmp.sv:91:+ assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
core/cache_subsystem/tag_cmp.sv:92:+ else begin
core/cache_subsystem/tag_cmp.sv:93:+ $fatal(1, "Hit should be one-hot encoded");
core/cache_subsystem/tag_cmp.sv:94:+ end
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format
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