doc PMP: rephrase PMP configuration description (#2540)

docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html

@@ -4395,10 +4395,10 @@ <h4 id="_physical_memory_protection_csrs">3.7.1. Physical Memory Protection CSRs
 </div>
 <div class="paragraph">
 <p>[CV32A65X] The PMP configuration registers are densely packed into CSRs to minimize
-context-switch time. For CV32A65X with sixty four CSRs, <code>pmpcfg0</code>–<code>pmpcfg15</code>, hold
-the configurations as shown
+context-switch time. For CV32A65X, sixteen CSRs, <code>pmpcfg0</code>–<code>pmpcfg15</code>, hold
+the configurations <code>pmp0cfg</code>–<code>pmp63cfg</code> for the 64 PMP entries, as shown
 in <a href="#pmpcfg-rv32">Figure 22</a>.
-The 14 upper entries are read-only zero.</p>
+The 14 upper PMP configuration CSRs, <code>pmpcfg2</code>-<code>pmpcfg15</code>, are read-only zero.</p>
 </div>
 <div id="pmpcfg-rv32" class="imageblock">
 <div class="content">
@@ -4411,7 +4411,8 @@ <h4 id="_physical_memory_protection_csrs">3.7.1. Physical Memory Protection CSRs
 PMP address register encodes bits 33-2 of a 34-bit physical address for
 RV32, as shown in <a href="#pmpaddr-rv32">Figure 23</a>. Not all
 physical address bits may be implemented, and so the <code>pmpaddr</code> registers
-are <strong>WARL</strong>.</p>
+are <strong>WARL</strong>.
+The 56 upper PMP address CSRs, <code>pmpaddr8</code>-<code>pmpaddr63</code>, are read-only zero.</p>
 </div>
 <div id="pmpaddr-rv32" class="imageblock">
 <div class="content">

docs/06_cv64a6_mmu/riscv/priv-isa-cv64a6_mmu.html

@@ -4656,10 +4656,10 @@ <h4 id="_physical_memory_protection_csrs">3.7.1. Physical Memory Protection CSRs
 </div>
 <div class="paragraph">
 <p>[CV64A6_MMU] The PMP configuration registers are densely packed into CSRs to minimize
-context-switch time. For CV64A6_MMU with sixty four CSRs, <code>pmpcfg0</code>–<code>pmpcfg15</code>, hold
-the configurations as shown
+context-switch time. For CV64A6_MMU, sixteen CSRs, <code>pmpcfg0</code>–<code>pmpcfg15</code>, hold
+the configurations <code>pmp0cfg</code>–<code>pmp63cfg</code> for the 64 PMP entries, as shown
 in <a href="#pmpcfg-rv32">Figure 25</a>.
-The 14 upper entries are read-only zero.</p>
+The 14 upper PMP configuration CSRs, <code>pmpcfg2</code>-<code>pmpcfg15</code>, are read-only zero.</p>
 </div>
 <div id="pmpcfg-rv32" class="imageblock">
 <div class="content">
@@ -4672,7 +4672,8 @@ <h4 id="_physical_memory_protection_csrs">3.7.1. Physical Memory Protection CSRs
 PMP address register encodes bits 33-2 of a 34-bit physical address for
 RV32, as shown in <a href="#pmpaddr-rv32">Figure 26</a>. Not all
 physical address bits may be implemented, and so the <code>pmpaddr</code> registers
-are <strong>WARL</strong>.</p>
+are <strong>WARL</strong>.
+The 56 upper PMP address CSRs, <code>pmpaddr8</code>-<code>pmpaddr63</code>, are read-only zero.</p>
 </div>
 <div id="pmpaddr-rv32" class="imageblock">
 <div class="content">

docs/riscv-isa/src/machine.adoc

@@ -4194,10 +4194,10 @@ implemented first. All PMP CSR fields are *WARL* and 56 upper entries are
 read-only zero. PMP CSRs are only accessible to M-mode.
 
 [{ohg-config}] The PMP configuration registers are densely packed into CSRs to minimize
-context-switch time. For {ohg-config} with sixty four CSRs, `pmpcfg0`–`pmpcfg15`, hold
-the configurations as shown
+context-switch time. For {ohg-config}, sixteen CSRs, `pmpcfg0`–`pmpcfg15`, hold
+the configurations `pmp0cfg`–`pmp63cfg` for the 64 PMP entries, as shown
 in <<pmpcfg-rv32>>.
-The 14 upper entries are read-only zero.
+The 14 upper PMP configuration CSRs, `pmpcfg2`-`pmpcfg15`, are read-only zero.
 
 [[pmpcfg-rv32]]
 .RV32 PMP configuration CSR layout.
@@ -4208,6 +4208,7 @@ PMP address register encodes bits 33-2 of a 34-bit physical address for
 RV32, as shown in <<pmpaddr-rv32>>. Not all
 physical address bits may be implemented, and so the `pmpaddr` registers
 are *WARL*.
+The 56 upper PMP address CSRs, `pmpaddr8`-`pmpaddr63`, are read-only zero.
 
 [[pmpaddr-rv32]]
 .PMP address register format, RV32.