Merge branch 'master' into tristan-verif-doc

openhwgroup · Oct 17, 2024 · a01a023 · a01a023
2 parents 6f6be9e + 7394941
commit a01a023
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Showing 26 changed files with 459 additions and 318 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -272,7 +272,7 @@ asic-synthesis:
     - echo $PERIOD
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -526,19 +526,21 @@ simu-gate:
     matrix:
       - SIMU_PERIOD: ["20"]  # 50 Mhz
         PERIOD:      ["15"]  # 66 Mhz
+        PROG_NAME:   "dhrystone"
   variables:
     DASHBOARD_JOB_TITLE: "Gate Level Simulation $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Tests to check netlist from ASIC synthesis and power consumption over different patterns"
     DASHBOARD_SORT_INDEX: 6
     DASHBOARD_JOB_CATEGORY: "Post Synthesis"
     DV_TARGET: cv32a65x
     TARGET: $DV_TARGET
+    SPIKE_TANDEM: 1
   script:
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
@@ -548,6 +550,7 @@ simu-gate:
     - mkdir -p pd/synth/cva6_${DV_TARGET}/outputs/
     - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=$PROG_NAME
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
+    - rm artifacts/artifacts_gate/*/build/*.fsdb
   after_script: *simu_after_script
 
 fpga-boot:

diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 171804
+  gates: 176232
diff --git a/core/cva6.sv b/core/cva6.sv
@@ -27,7 +27,7 @@ module cva6
     parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg),
     parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg),
     parameter type rvfi_probes_t = struct packed {
-      logic csr;
+      rvfi_probes_csr_t   csr;
       rvfi_probes_instr_t instr;
     },
 

diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv
@@ -158,11 +158,9 @@ module bht #(
       bht = '0;
 
       for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
-        if (row_index == i) begin
-          bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
-          bht_prediction_o[i].valid = bht_ram_rdata_0[i*BRAM_WORD_BITS+2];
-          bht_prediction_o[i].taken = bht_ram_rdata_0[i*BRAM_WORD_BITS+1];
-        end
+        bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index;
+        bht_prediction_o[i].valid = bht_ram_rdata_0[i*BRAM_WORD_BITS+2];
+        bht_prediction_o[i].taken = bht_ram_rdata_0[i*BRAM_WORD_BITS+1];
       end
 
       if (bht_update_i.valid && !debug_mode_i) begin

diff --git a/verif/env/corev-dv/cva6_asm_program_gen.sv b/verif/env/corev-dv/cva6_asm_program_gen.sv
@@ -175,7 +175,7 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
     end else begin
       // Push user mode GPR to kernel stack before executing exception handling, this is to avoid
       // exception handling routine modify user program state unexpectedly
-      push_used_gpr_to_kernel_stack(status, scratch, 4, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
+      push_used_gpr_to_kernel_stack(status, scratch, 3, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
       // Checking xStatus can be optional if ISS (like spike) has different implementation of
       // certain fields compared with the RTL processor.
       if (cfg_cva6.check_xstatus) begin
@@ -187,16 +187,19 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
                // Check if the exception is caused by an interrupt, if yes, jump to interrupt
                // handler Interrupt is indicated by xCause[XLEN-1]
                $sformatf("csrr x%0d, 0x%0x # %0s", cfg_cva6.gpr[0], cause, cause.name()),
+               $sformatf("srli x%0d, x%0d, %0d", cfg_cva6.gpr[0], cfg_cva6.gpr[0], XLEN-1),
+               $sformatf("bne x%0d, x0, %0s%0s_intr_handler",
+                         cfg_cva6.gpr[0], hart_prefix(hart), mode),
                $sformatf("csrr  x%0d, mepc", cfg_cva6.gpr[0]),
-               $sformatf("lbu  x%0d, 0(x%0d)", cfg_cva6.gpr[3],cfg_cva6.gpr[0]),
+               $sformatf("lbu  x%0d, 0(x%0d)", cfg_cva6.gpr[2],cfg_cva6.gpr[0]),
                $sformatf("li  x%0d, 0x3", cfg_cva6.gpr[1]),
-               $sformatf("and  x%0d, x%0d, x%0d", cfg_cva6.gpr[3], cfg_cva6.gpr[3], cfg_cva6.gpr[1]),
-               $sformatf("bne  x%0d, x%0d, exception_handler_incr_mepc2", cfg_cva6.gpr[3], cfg_cva6.gpr[1]),
+               $sformatf("and  x%0d, x%0d, x%0d", cfg_cva6.gpr[2], cfg_cva6.gpr[2], cfg_cva6.gpr[1]),
+               $sformatf("bne  x%0d, x%0d, exception_handler_incr_mepc2", cfg_cva6.gpr[2], cfg_cva6.gpr[1]),
                $sformatf("addi  x%0d, x%0d, 2", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
                str,
                $sformatf("addi  x%0d, x%0d, 2", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
                $sformatf("csrw  mepc, x%0d", cfg_cva6.gpr[0])};
-      pop_used_gpr_from_kernel_stack(MSTATUS, MSCRATCH, 4, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr);
+      pop_used_gpr_from_kernel_stack(MSTATUS, MSCRATCH, 3, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
       instr.push_back("mret");
     end
     // The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
@@ -213,7 +216,49 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
     if (cfg_cva6.mtvec_mode == VECTORED) begin
       push_gpr_to_kernel_stack(status, scratch, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
     end
-    gen_signature_handshake(instr, CORE_STATUS, HANDLING_EXCEPTION);
+    //~ push_used_gpr_to_kernel_stack(status, scratch, 3, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
+    instr = {instr,
+             // The trap is caused by an exception, read back xCAUSE, xEPC to see if these
+             // CSR values are set properly.
+             $sformatf("csrr x%0d, 0x%0x # %0s", cfg_cva6.gpr[0], epc, epc.name()),
+             $sformatf("csrr x%0d, 0x%0x # %0s", cfg_cva6.gpr[0], cause, cause.name()),
+             $sformatf("li x%0d, 0x8000000b", cfg_cva6.gpr[1]),
+             $sformatf("li x%0d, 0x80000007", cfg_cva6.gpr[2]),
+             $sformatf("beq x%0d, x%0d, ext_interrupt_handler", cfg_cva6.gpr[0], cfg_cva6.gpr[1]),
+             $sformatf("beq x%0d, x%0d, timer_interrupt_handler", cfg_cva6.gpr[0], cfg_cva6.gpr[2]),
+             $sformatf("j test_done")
+             };
+    gen_section(get_label($sformatf("%0s_intr_handler", mode), hart), instr);
+
+    instr = {};
+    instr = {instr,
+             // The trap is caused by an external interrupt, read back xIP
+             // Write into int_ack 0x1 value
+             $sformatf("csrr x%0d, 0x%0x # %0s", cfg_cva6.gpr[0], epc, ip.name()),
+             $sformatf("li x%0d, 0", cfg_cva6.gpr[0]),
+             $sformatf("addi x%0d, x%0d, 1", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
+             // Clean external pending interrupt
+             $sformatf("sw x%0d, int_ack, x%0d # %0s;",
+                       cfg_cva6.gpr[0], cfg_cva6.gpr[1], ip.name())
+             };
+    pop_used_gpr_from_kernel_stack(MSTATUS, MSCRATCH, 3, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
+    instr.push_back("mret");
+    gen_section(get_label($sformatf("ext_interrupt_handler"), hart), instr);
+
+    instr = {};
+    instr = {instr,
+             // The trap is caused by a timer interrupt, read back xIP
+             // Write into int_ack 0x2 value
+             $sformatf("csrr x%0d, 0x%0x # %0s", cfg_cva6.gpr[0], epc, ip.name()),
+             $sformatf("li x%0d, 0", cfg_cva6.gpr[0]),
+             $sformatf("addi x%0d, x%0d, 2", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
+             // Clean timer pending interrupt
+             $sformatf("sw x%0d, int_ack, x%0d",
+                       cfg_cva6.gpr[0], cfg_cva6.gpr[1])
+             };
+    pop_used_gpr_from_kernel_stack(MSTATUS, MSCRATCH, 3, cfg_cva6.mstatus_mprv, cfg_cva6.sp, cfg_cva6.tp, instr);
+    instr.push_back("mret");
+    gen_section(get_label($sformatf("timer_interrupt_handler"), hart), instr);
   endfunction
 
   // Push used general purpose register to stack, this is needed before trap handling
@@ -314,31 +359,31 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
                                         test_result_t test_result = TEST_FAIL,
                                         privileged_reg_t csr = MSCRATCH,
                                         string addr_label = "");
-    if (cfg.require_signature_addr) begin
+    if (cfg_cva6.require_signature_addr) begin
       string str[$];
-      str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[1], cfg.signature_addr)};
+      str = {$sformatf("li x%0d, 0x%0h", cfg_cva6.gpr[1], cfg_cva6.signature_addr)};
       instr = {instr, str};
       case (signature_type)
         // A single data word is written to the signature address.
         // Bits [7:0] contain the signature_type of CORE_STATUS, and the upper
         // XLEN-8 bits contain the core_status_t data.
         CORE_STATUS: begin
-          str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], core_status),
-                 $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]),
-                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0],
-                           cfg.gpr[0], signature_type),
-                 $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])};
+          str = {$sformatf("li x%0d, 0x%0h", cfg_cva6.gpr[0], core_status),
+                 $sformatf("slli x%0d, x%0d, 8", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
+                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg_cva6.gpr[0],
+                           cfg_cva6.gpr[0], signature_type),
+                 $sformatf("sw x%0d, 0(x%0d)", cfg_cva6.gpr[0], cfg_cva6.gpr[1])};
           instr = {instr, str};
         end
         // A single data word is written to the signature address.
         // Bits [7:0] contain the signature_type of TEST_RESULT, and the upper
         // XLEN-8 bits contain the test_result_t data.
         TEST_RESULT: begin
-          str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], test_result),
-                 $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]),
-                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0],
-                           cfg.gpr[0], signature_type),
-                 $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])};
+          str = {$sformatf("li x%0d, 0x%0h", cfg_cva6.gpr[0], test_result),
+                 $sformatf("slli x%0d, x%0d, 8", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
+                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg_cva6.gpr[0],
+                           cfg_cva6.gpr[0], signature_type),
+                 $sformatf("sw x%0d, 0(x%0d)", cfg_cva6.gpr[0], cfg_cva6.gpr[1])};
           instr = {instr, str};
         end
         // The first write to the signature address contains just the
@@ -347,11 +392,11 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
         // each writing the data contained in one GPR, starting from x0 as the
         // first write, and ending with x31 as the 32nd write.
         WRITE_GPR: begin
-          str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], signature_type),
-                 $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])};
+          str = {$sformatf("li x%0d, 0x%0h", cfg_cva6.gpr[0], signature_type),
+                 $sformatf("sw x%0d, 0(x%0d)", cfg_cva6.gpr[0], cfg_cva6.gpr[1])};
           instr = {instr, str};
           for(int i = 0; i < 32; i++) begin
-            str = {$sformatf("sw x%0x, 0(x%0d)", i, cfg.gpr[1])};
+            str = {$sformatf("sw x%0x, 0(x%0d)", i, cfg_cva6.gpr[1])};
             instr = {instr, str};
           end
         end
@@ -364,13 +409,13 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
           if (!(csr inside {implemented_csr})) begin
             return;
           end
-          str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], csr),
-                 $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]),
-                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0],
-                           cfg.gpr[0], signature_type),
-                 $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1]),
-                 $sformatf("csrr x%0d, 0x%0h", cfg.gpr[0], csr),
-                 $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])};
+          str = {$sformatf("li x%0d, 0x%0h", cfg_cva6.gpr[0], csr),
+                 $sformatf("slli x%0d, x%0d, 8", cfg_cva6.gpr[0], cfg_cva6.gpr[0]),
+                 $sformatf("addi x%0d, x%0d, 0x%0h", cfg_cva6.gpr[0],
+                           cfg_cva6.gpr[0], signature_type),
+                 $sformatf("sw x%0d, 0(x%0d)", cfg_cva6.gpr[0], cfg_cva6.gpr[1]),
+                 $sformatf("csrr x%0d, 0x%0h", cfg_cva6.gpr[0], csr),
+                 $sformatf("sw x%0d, 0(x%0d)", cfg_cva6.gpr[0], cfg_cva6.gpr[1])};
           instr = {instr, str};
         end
         default: begin
@@ -385,9 +430,19 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen;
       instr_stream.push_back(str);
       instr_stream.push_back({indent, "li gp, 1"});
       instr_stream.push_back({indent, "sw gp, tohost, t5"});
-      instr_stream.push_back({indent, "wfi"});
+      instr_stream.push_back({indent, "end_of_test: j end_of_test"});
    endfunction
 
+
+  virtual function void gen_data_page_begin(int hart);
+    instr_stream.push_back(".section .data");
+    if (hart == 0) begin
+      instr_stream.push_back(".align 6; .global tohost; tohost: .dword 0;");
+      instr_stream.push_back(".align 6; .global fromhost; fromhost: .dword 0;");
+      instr_stream.push_back(".align 6; .global int_ack; int_ack: .dword 0;");
+    end
+  endfunction
+
 endclass : cva6_asm_program_gen_c
 
 `endif // __CVA6_ASM_PROGRAM_GEN_SV__
diff --git a/verif/env/uvme/cov/uvme_interrupt_covg.sv b/verif/env/uvme/cov/uvme_interrupt_covg.sv
@@ -19,7 +19,8 @@
 // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com)
 
 covergroup cg_interrupt(
-    string name
+    string name,
+    bit sw_int_supported
 ) with function sample (
     uvma_isacov_instr_c instr
 );
@@ -29,6 +30,7 @@ covergroup cg_interrupt(
   cp_interrupt: coverpoint instr.rvfi.name_csrs["mcause"].wdata {
     bins NO_INTERRUPT = {0} iff (!instr.trap);
 
+    ignore_bins IGN_SOFTWARE_INTERRUPT   = {32'h80000003} iff (!sw_int_supported);
     bins MACHINE_MODE_EXTERNAL_INTERRUPT = {32'h8000000b} iff (instr.trap);
     bins MACHINE_MODE_SOFTWARE_INTERRUPT = {32'h80000003} iff (instr.trap);
     bins MACHINE_MODE_TIMER_INTERRUPT    = {32'h80000007} iff (instr.trap);
@@ -40,6 +42,7 @@ covergroup cg_interrupt(
    }
 
   cp_msie: coverpoint instr.rvfi.name_csrs["mie"].wdata[3] {
+    ignore_bins IGN_MSIE = {1'h1} iff (!sw_int_supported);
     bins MSIE = {1'h1};
    }
 
@@ -52,6 +55,7 @@ covergroup cg_interrupt(
    }
 
   cp_msip: coverpoint instr.rvfi.name_csrs["mip"].wdata[3] {
+    ignore_bins IGN_MSIP = {1'h1} iff (!sw_int_supported);
     bins MSIP = {1'h1};
    }
 
@@ -106,8 +110,8 @@ function void uvme_interrupt_covg_c::build_phase(uvm_phase phase);
    end
 
    if (!cfg.disable_all_csr_checks)
-      interrupt_cg = new("interrupt_cg");
-   else
+      interrupt_cg = new("interrupt_cg",
+                         .sw_int_supported(cfg.sw_int_supported));   else
       `uvm_warning(get_type_name(), "Interrupt coverage will not be scored since config disable_all_csr_checks is true")
 
    mon_trn_fifo   = new("mon_trn_fifo" , this);
@@ -127,4 +131,3 @@ task uvme_interrupt_covg_c::run_phase(uvm_phase phase);
      end
 
 endtask : run_phase
-
diff --git a/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv b/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv
@@ -12,14 +12,17 @@
 `define __UVMA_INTERRUPT_COV_MODEL_SV__
 
 covergroup cg_interrupt(
-    string name
+    string name,
+    int unsigned num_irq_supported
     ) with function
     sample(uvma_interrupt_seq_item_c req_item);
 
     option.per_instance = 1;
     option.name = name;
 
-   cp_interrupt_req :   coverpoint req_item.interrupt_valid;
+   cp_interrupt_req : coverpoint req_item.interrupt_vector {
+      bins INTERRUPTS[] = {[0:$]} with (item inside {[0:(2**(num_irq_supported))-1]});
+   }
 
 endgroup: cg_interrupt
 
@@ -77,15 +80,16 @@ function void uvma_interrupt_cov_model_c::build_phase(uvm_phase phase);
 
    void'(uvm_config_db#(uvma_interrupt_cfg_c)::get(this, "", "cfg", cfg));
    if (cfg == null) begin
-      `uvm_fatal("CFG", "Configuration handle is null")
+      `uvm_fatal(get_type_name(), "Configuration handle is null")
    end
 
    void'(uvm_config_db#(uvma_interrupt_cntxt_c)::get(this, "", "cntxt", cntxt));
    if (cntxt == null) begin
-      `uvm_fatal("CNTXT", "Context handle is null")
+      `uvm_fatal(get_type_name(), "Context handle is null")
    end
 
-   interrupt_cg = new("interrupt_cg");
+   interrupt_cg = new("interrupt_cg",
+                      .num_irq_supported(cfg.num_irq_supported));
 
    seq_item_fifo = new("seq_item_fifo", this);