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Support multiple outstanding load operations to the Dcache (#1348)
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This modification introduces a pending load table that tracks outstanding load operations to the Dcache. The depth of this table is a parameter in the target configuration package.
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@JeanRochCoulon
JeanRochCoulon authored Sep 2, 2023
2 parents c8202ae + 85b3898 commit d9ad16b
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Showing 17 changed files with 349 additions and 228 deletions.
2 changes: 1 addition & 1 deletion .gitlab-ci/expected_synth.yml
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Expand Up @@ -3,4 +3,4 @@ cv64a6_imafdc_sv39:
cv32a60x:
gates: 160719
cv32a6_embedded:
gates: 127613
gates: 127977
6 changes: 5 additions & 1 deletion core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -74,6 +74,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
typedef struct packed {
logic [DCACHE_INDEX_WIDTH-1:0] index;
logic [DCACHE_TAG_WIDTH-1:0] tag;
logic [DCACHE_TID_WIDTH-1:0] id;
logic [7:0] be;
logic [1:0] size;
logic we;
Expand Down Expand Up @@ -116,7 +117,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
req_port_o.data_gnt = 1'b0;
req_port_o.data_rvalid = 1'b0;
req_port_o.data_rdata = '0;
req_port_o.data_rid = '0;
req_port_o.data_rid = mem_req_q.id;
miss_req_o = '0;
mshr_addr_o = '0;
// Memory array communication
Expand All @@ -138,6 +139,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(

// save index, be and we
mem_req_d.index = req_port_i.address_index;
mem_req_d.id = req_port_i.data_id;
mem_req_d.be = req_port_i.data_be;
mem_req_d.size = req_port_i.data_size;
mem_req_d.we = req_port_i.data_we;
Expand Down Expand Up @@ -186,6 +188,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
if (req_port_i.data_req && !mem_req_q.we && !flush_i) begin
state_d = WAIT_TAG; // switch back to WAIT_TAG
mem_req_d.index = req_port_i.address_index;
mem_req_d.id = req_port_i.data_id;
mem_req_d.be = req_port_i.data_be;
mem_req_d.size = req_port_i.data_size;
mem_req_d.we = req_port_i.data_we;
Expand Down Expand Up @@ -391,6 +394,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
if (req_port_i.data_req) begin
// save index, be and we
mem_req_d.index = req_port_i.address_index;
mem_req_d.id = req_port_i.data_id;
mem_req_d.be = req_port_i.data_be;
mem_req_d.size = req_port_i.data_size;
mem_req_d.we = req_port_i.data_we;
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6 changes: 5 additions & 1 deletion core/cache_subsystem/wt_dcache_ctrl.sv
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Expand Up @@ -59,6 +59,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
logic [DCACHE_TAG_WIDTH-1:0] address_tag_d, address_tag_q;
logic [DCACHE_CL_IDX_WIDTH-1:0] address_idx_d, address_idx_q;
logic [DCACHE_OFFSET_WIDTH-1:0] address_off_d, address_off_q;
logic [DCACHE_TID_WIDTH-1:0] id_d, id_q;
logic [DCACHE_SET_ASSOC-1:0] vld_data_d, vld_data_q;
logic save_tag, rd_req_d, rd_req_q, rd_ack_d, rd_ack_q;
logic [1:0] data_size_d, data_size_q;
Expand All @@ -72,14 +73,15 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
assign address_tag_d = (save_tag) ? req_port_i.address_tag : address_tag_q;
assign address_idx_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH] : address_idx_q;
assign address_off_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_OFFSET_WIDTH-1:0] : address_off_q;
assign id_d = (req_port_o.data_gnt) ? req_port_i.data_id : id_q;
assign data_size_d = (req_port_o.data_gnt) ? req_port_i.data_size : data_size_q;
assign rd_tag_o = address_tag_d;
assign rd_idx_o = address_idx_d;
assign rd_off_o = address_off_d;

assign req_port_o.data_rdata = rd_data_i;
assign req_port_o.data_ruser = rd_user_i;
assign req_port_o.data_rid = '0;
assign req_port_o.data_rid = id_q;

// to miss unit
assign miss_vld_bits_o = vld_data_q;
Expand Down Expand Up @@ -240,6 +242,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
address_tag_q <= '0;
address_idx_q <= '0;
address_off_q <= '0;
id_q <= '0;
vld_data_q <= '0;
data_size_q <= '0;
rd_req_q <= '0;
Expand All @@ -249,6 +252,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
address_tag_q <= address_tag_d;
address_idx_q <= address_idx_d;
address_off_q <= address_off_d;
id_q <= id_d;
vld_data_q <= vld_data_d;
data_size_q <= data_size_d;
rd_req_q <= rd_req_d;
Expand Down
1 change: 1 addition & 0 deletions core/cva6.sv
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Expand Up @@ -168,6 +168,7 @@ module cva6 import ariane_pkg::*; #(
CVA6Cfg.AxiDataWidth,
CVA6Cfg.AxiIdWidth,
CVA6Cfg.AxiUserWidth,
CVA6Cfg.NrLoadBufEntries,
CVA6Cfg.FpuEn,
CVA6Cfg.XF16,
CVA6Cfg.XF16ALT,
Expand Down
3 changes: 3 additions & 0 deletions core/include/config_pkg.sv
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Expand Up @@ -21,6 +21,7 @@ package config_pkg;
int unsigned AxiDataWidth;
int unsigned AxiIdWidth;
int unsigned AxiUserWidth;
int unsigned NrLoadBufEntries;
bit FpuEn;
bit XF16;
bit XF16ALT;
Expand Down Expand Up @@ -51,6 +52,7 @@ package config_pkg;
unsigned'(64), // AxiDataWidth
unsigned'(4), // AxiIdWidth
unsigned'(32), // AxiUserWidth
unsigned'(2), // NrLoadBufEntries
bit'(0), // FpuEn
bit'(0), // XF16
bit'(0), // XF16ALT
Expand Down Expand Up @@ -81,6 +83,7 @@ package config_pkg;
unsigned'(0), // AxiDataWidth
unsigned'(0), // AxiIdWidth
unsigned'(0), // AxiUserWidth
unsigned'(0), // NrLoadBufEntries
bit'(0), // FpuEn
bit'(0), // XF16
bit'(0), // XF16ALT
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a60x_config_pkg.sv
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Expand Up @@ -58,6 +58,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigInstrTlbEntries = 2;
localparam CVA6ConfigDataTlbEntries = 2;
Expand All @@ -77,20 +78,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a6_embedded_config_pkg.sv
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Expand Up @@ -57,6 +57,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigInstrTlbEntries = 2;
localparam CVA6ConfigDataTlbEntries = 2;
Expand All @@ -76,20 +77,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigInstrTlbEntries = 2;
localparam CVA6ConfigDataTlbEntries = 2;
Expand All @@ -77,20 +78,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a6_imac_sv0_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigFPGAEn = 0;

Expand All @@ -77,20 +78,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a6_imac_sv32_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigInstrTlbEntries = 2;
localparam CVA6ConfigDataTlbEntries = 2;
Expand All @@ -77,20 +78,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
30 changes: 16 additions & 14 deletions core/include/cv32a6_imafc_sv32_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,7 @@ package cva6_config_pkg;

localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigInstrTlbEntries = 2;
localparam CVA6ConfigDataTlbEntries = 2;
Expand All @@ -77,20 +78,21 @@ package cva6_config_pkg;
localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
// Extended
bit'(0), // RVF
bit'(0), // RVD
Expand Down
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