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Draft HPDIcache (extended hpdcache) #2506

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Draft HPDIcache (extended hpdcache) #2506

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2489e4c
wip: end of gsoc
takeshiho0531 Sep 23, 2024
54d0abc
fix: hpdcache version
takeshiho0531 Sep 24, 2024
6208e7b
fix: grant logic in hpdicache_adapter
takeshiho0531 Sep 24, 2024
0b94788
fix: obi grant signal logic in hpdicache adapter
takeshiho0531 Sep 24, 2024
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1 change: 1 addition & 0 deletions core/Flist.cva6
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Original file line number Diff line number Diff line change
Expand Up @@ -184,6 +184,7 @@ ${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_write.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_wrapper.sv
${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv
${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv
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99 changes: 66 additions & 33 deletions core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Authors: Akiho Kawada
// Date: June, 2024
// Date: July, 2024
// Description: Icache Interface adapter for the CVA6 core
module cva6_hpdcache_icache_if_adapter
// Parameters
Expand All @@ -24,7 +24,7 @@ module cva6_hpdcache_icache_if_adapter
parameter type fetch_drsp_t = logic,
parameter type obi_fetch_req_t = logic,
parameter type obi_fetch_rsp_t = logic,
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 0
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 0 // TODO
)
// }}}

Expand All @@ -39,10 +39,10 @@ module cva6_hpdcache_icache_if_adapter
input hpdcache_req_sid_t hpdcache_req_sid_i,

// Request/response ports from/to the CVA6 core
input fetch_dreq_t fetch_dreq_i,
output fetch_drsp_t fetch_dreq_o,
input obi_fetch_req_t obi_fetch_req_i,
output obi_fetch_rsp_t obi_fetch_rsp_o,
input fetch_dreq_t dreq_i,
output fetch_drsp_t dreq_o,
input obi_fetch_req_t fetch_obi_req_i,
output obi_fetch_rsp_t fetch_obi_rsp_o,

// Request port to the L1 Dcache
output logic hpdcache_req_valid_o,
Expand All @@ -58,67 +58,100 @@ module cva6_hpdcache_icache_if_adapter
);
// }}}

// Internal nets and registers
// {{{
logic hpdcache_req_is_uncacheable;
// localparam ICACHE_OFFSET_WIDTH = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8);
localparam ICACHE_OFFSET_WIDTH = 3;
localparam int ICACHE_CL_SIZE = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8);
localparam int ICACHE_WORD_SIZE = 3;
localparam int ICACHE_MEM_REQ_CL_SIZE =
(CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH) ?
$clog2(
CVA6Cfg.AxiDataWidth / 8
) : ICACHE_CL_SIZE;

// Internal nets and registers
// {{{
logic hpdcache_req_is_uncacheable;
logic va_transferred_q, va_transferred_d;

always_ff @(posedge clk_i or negedge rst_ni) begin : transferred_state_magnegement
if (!rst_ni) begin
va_transferred_q <= '0;
end else begin
va_transferred_q <= va_transferred_d;
end
end

assign va_transferred_d = dreq_i.req & hpdcache_req_ready_i;
// }}}

// Request forwarding
// {{{
// LOAD request
// {{{

assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions(
CVA6Cfg,
{
{64 - CVA6Cfg.PLEN{1'b0}},
obi_fetch_req_i.a.addrr[CVA6Cfg.ICACHE_TAG_WIDTH+CVA6Cfg.ICACHE_INDEX_WIDTH-1:CVA6Cfg.ICACHE_INDEX_WIDTH],
fetch_obi_req_i.a.addr[CVA6Cfg.ICACHE_TAG_WIDTH+CVA6Cfg.ICACHE_INDEX_WIDTH-1:CVA6Cfg.ICACHE_INDEX_WIDTH], // TODO
{CVA6Cfg.ICACHE_INDEX_WIDTH{1'b0}}
}
);

// Request forwarding
assign hpdcache_req_valid_o = fetch_dreq_i.data_req,
hpdcache_req_o.addr_offset = fetch_dreq_i.vaddr[CVA6Cfg.ICACHE_INDEX_WIDTH-1:3],
assign hpdcache_req_valid_o = dreq_i.req,
hpdcache_req_o.addr_offset = dreq_i.vaddr[CVA6Cfg.ICACHE_INDEX_WIDTH-1:0],
hpdcache_req_o.wdata = '0,
hpdcache_req_o.op = hpdcache_pkg::HPDCACHE_REQ_LOAD,
hpdcache_req_o.be = obi_fetch_req_i.a.data_be,
hpdcache_req_o.size = hpdcache_req_is_uncacheable ? ICACHE_WORD_SIZE : ICACHE_MEM_REQ_CL_SIZE,
hpdcache_req_o.be = fetch_obi_req_i.a.be,
hpdcache_req_o.size = hpdcache_req_is_uncacheable ? ICACHE_WORD_SIZE : ICACHE_MEM_REQ_CL_SIZE, // TODO
hpdcache_req_o.sid = '0,
hpdcache_req_o.tid = RdTxId, // TODO
hpdcache_req_o.tid = RdTxId, // TODO
hpdcache_req_o.need_rsp = 1'b1,
hpdcache_req_o.phys_indexed = 1'b0,
hpdcache_req_o.addr_tag = '0, // unused on virtually indexed request
hpdcache_req_o.pma = '0; // unused on virtually indexed request

assign hpdcache_req_abort_o = fetch_dreq_i.kill_req,
hpdcache_req_tag_o = obi_fetch_req_i.a.addrr[CVA6Cfg.ICACHE_TAG_WIDTH+CVA6Cfg.ICACHE_INDEX_WIDTH-1:CVA6Cfg.ICACHE_INDEX_WIDTH],
assign hpdcache_req_abort_o = va_transferred_q & (dreq_i.kill_req | ~fetch_obi_req_i.req),
hpdcache_req_tag_o = fetch_obi_req_i.a.addr[CVA6Cfg.ICACHE_TAG_WIDTH+CVA6Cfg.ICACHE_INDEX_WIDTH-1:CVA6Cfg.ICACHE_INDEX_WIDTH],
hpdcache_req_pma_o.uncacheable = hpdcache_req_is_uncacheable,
hpdcache_req_pma_o.io = 1'b0;

// Response forwarding
assign cva6_req_o.data_rvalid = hpdcache_rsp_valid_i,
cva6_req_o.data_rdata = hpdcache_rsp_i.rdata,
cva6_req_o.data_rid = hpdcache_rsp_i.tid,
cva6_req_o.data_gnt = hpdcache_req_ready_i;

assign fetch_obi_rsp_o.gnt = hpdcache_req_ready_i, // TODO
fetch_obi_rsp_o.gntpar = !hpdcache_req_ready_i, // TODO
fetch_obi_rsp_o.rvalid = hpdcache_rsp_valid_i, // TODO
fetch_obi_rsp_o.rvalidpar = !hpdcache_rsp_valid_i, // TODO
fetch_obi_rsp_o.r.rid = '0,
assign dreq_o.ready = hpdcache_req_ready_i;
logic obi_gnt_q, obi_gnt_d; // TODO

assign obi_gnt_d = dreq_i.req;

always_ff @(posedge clk_i or negedge rst_ni) begin : obi_gnt_gen
if (!rst_ni) begin
obi_gnt_q <= '0;
end else begin
obi_gnt_q <= obi_gnt_d;
end
end

logic which_half_d, which_half_q;
assign which_half_d = (fetch_obi_req_i.req) ? fetch_obi_req_i.a.addr[2] : which_half_q;


always_ff @(posedge clk_i or negedge rst_ni) begin : gen_offset
if (!rst_ni) begin
which_half_q <= '0;
end else begin
which_half_q <= which_half_d;
end
end

assign fetch_obi_rsp_o.gnt = obi_gnt_q,
fetch_obi_rsp_o.gntpar = !obi_gnt_q,
fetch_obi_rsp_o.rvalid = hpdcache_rsp_valid_i,
fetch_obi_rsp_o.rvalidpar = !hpdcache_rsp_valid_i,
fetch_obi_rsp_o.r.rid = hpdcache_rsp_i.tid,
fetch_obi_rsp_o.r.r_optional.exokay = '0,
fetch_obi_rsp_o.r.r_optional.rchk = '0,
fetch_obi_rsp_o.r.err = '0,
fetch_obi_rsp_o.r.rdata = hpdcache_rsp_i.rdata,
fetch_obi_rsp_o.r.r_optional.ruser = '0;
fetch_obi_rsp_o.r.err = hpdcache_rsp_i.error,
fetch_obi_rsp_o.r.rdata = hpdcache_rsp_i.rdata[0][{
which_half_q, 5'b0
}+:CVA6Cfg.FETCH_WIDTH],
fetch_obi_rsp_o.r.r_optional.ruser = '0; // TODO
// }}}
// }}}

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