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Merge pull request #282 from ross144/main
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Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
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@davidharrishmc
davidharrishmc authored Apr 27, 2023
2 parents 4f6c493 + e72fa0c commit e43de9c
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48 changes: 48 additions & 0 deletions fpga/constraints/artyddr3.ucf
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NET "ddr3_dq[0]" LOC = "K5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[1]" LOC = "L3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[2]" LOC = "K3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[3]" LOC = "L6" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[4]" LOC = "M3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[5]" LOC = "M1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[6]" LOC = "L4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[7]" LOC = "M2" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[8]" LOC = "V4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[9]" LOC = "T5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[10]" LOC = "U4" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[11]" LOC = "V5" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[12]" LOC = "V1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[13]" LOC = "T3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[14]" LOC = "U3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dq[15]" LOC = "R3" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[0]" LOC = "L1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dm[1]" LOC = "U1" | IOSTANDARD = SSTL15 ;
NET "ddr3_dqs_p[0]" LOC = "N2" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[0]" LOC = "N1" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_addr[13]" LOC = "T8" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[12]" LOC = "T6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[11]" LOC = "U6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[10]" LOC = "R6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[9]" LOC = "V7" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[8]" LOC = "R8" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[7]" LOC = "U7" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[6]" LOC = "V6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[5]" LOC = "R7" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[4]" LOC = "N6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[3]" LOC = "T1" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[2]" LOC = "N4" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[1]" LOC = "M6" | IOSTANDARD = SSTL15 ;
NET "ddr3_addr[0]" LOC = "R2" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[2]" LOC = "P2" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[1]" LOC = "P4" | IOSTANDARD = SSTL15 ;
NET "ddr3_ba[0]" LOC = "R1" | IOSTANDARD = SSTL15 ;
NET "ddr3_ck_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_ck_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL15 ;
NET "ddr3_ras_n" LOC = "P3" | IOSTANDARD = SSTL15 ;
NET "ddr3_cas_n" LOC = "M4" | IOSTANDARD = SSTL15 ;
NET "ddr3_we_n" LOC = "P5" | IOSTANDARD = SSTL15 ;
NET "ddr3_reset_n" LOC = "K6" | IOSTANDARD = LVCMOS15 ;
NET "ddr3_cke[0]" LOC = "N5" | IOSTANDARD = SSTL15 ;
NET "ddr3_odt[0]" LOC = "R5" | IOSTANDARD = SSTL15 ;
NET "ddr3_cs_n[0]" LOC = "U8" | IOSTANDARD = SSTL15 ;
122 changes: 45 additions & 77 deletions fpga/constraints/constraints-artyA7.xdc → fpga/constraints/constraints-ArtyA7.xdc
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Original file line number Diff line number Diff line change
@@ -1,21 +1,25 @@
# The main clocks are all autogenerated by the Xilinx IP
# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.

create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]

##### clock #####
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]

##### GPI ####
set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
set_max_delay -from [get_ports {GPI[*]}] 10.000

##### GPO ####
Expand All @@ -24,77 +28,48 @@ set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
set_max_delay -to [get_ports {GPO[*]}] 10.000
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]


##### UART #####
# *** IOSTANDARD is probably wrong
set_property PACKAGE_PIN A9 [get_ports UARTSin]
set_property PACKAGE_PIN D0 [get_ports UARTSout]
set_max_delay -from [get_ports UARTSin] 10.000
set_max_delay -to [get_ports UARTSout] 10.000
set_property PACKAGE_PIN D10 [get_ports UARTSout]
set_max_delay -from [get_ports UARTSin] 14.000
set_max_delay -to [get_ports UARTSout] 14.000
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS3 [get_ports UARTSout]
set_property DRIVE 6 [get_ports UARTSout]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
set_property DRIVE 4 [get_ports UARTSout]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]


##### reset #####
#************** reset is inverted
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
set_max_delay -from [get_ports reset] 15.000
set_false_path -from [get_ports reset]
set_property PACKAGE_PIN C2 [get_ports {reset}]
set_property IOSTANDARD LVCMOS33 [get_ports {reset}]



##### cpu_reset #####
# ***********
set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]


##### calib #####
# **********
set_property PACKAGE_PIN BA37 [get_ports calib]
set_property IOSTANDARD LVCMOS12 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000

set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
set_max_delay -from [get_ports resetn] 15.000
set_false_path -from [get_ports resetn]
set_property PACKAGE_PIN C2 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]

##### ahblite_resetn #####
# ***************
set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]

set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
set_max_delay -from [get_ports south_reset] 15.000
set_false_path -from [get_ports south_reset]
set_property PACKAGE_PIN D9 [get_ports {south_reset}]
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]

##### south_rst #####
# ***********************
set_property PACKAGE_PIN BE22 [get_ports south_rst]
set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]


##### SD Card I/O #####
Expand All @@ -103,7 +78,7 @@ set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
set_property PACKAGE_PIN F2 [get_ports SDCCLK]
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]

set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
Expand Down Expand Up @@ -132,8 +107,8 @@ set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_por
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]

# *********************************
set_property DCI_CASCADE {64} [get_iobanks 65]
set_property INTERNAL_VREF 0.9 [get_iobanks 65]
#set_property DCI_CASCADE {64} [get_iobanks 65]
#set_property INTERNAL_VREF 0.9 [get_iobanks 65]

# ddr3

Expand Down Expand Up @@ -237,15 +212,8 @@ set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]



set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000


set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]



set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
# **** may have to bring this one back
#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000


set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK]
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