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Integrate LLVM at llvm/llvm-project@33363521ca24
Updates LLVM usage to match [33363521ca24](llvm/llvm-project@33363521ca24) PiperOrigin-RevId: 689288723
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,43 +1 @@ | ||
Auto generated patch. Do not edit or delete it, even if empty. | ||
diff -ruN --strip-trailing-cr a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
@@ -50049,8 +50049,9 @@ | ||
SDValue X, Y, Z; | ||
if (sd_match(N, m_And(m_Value(X), | ||
m_OneUse(m_Or(m_Value(Y), m_Not(m_Value(Z))))))) { | ||
- // Don't fold if Y is a constant to prevent infinite loops. | ||
- if (!isa<ConstantSDNode>(Y)) | ||
+ // Don't fold if Y or Z are constants to prevent infinite loops. | ||
+ if (!DAG.isConstantIntBuildVectorOrConstantInt(Y) && | ||
+ !DAG.isConstantIntBuildVectorOrConstantInt(Z)) | ||
return DAG.getNode( | ||
ISD::AND, DL, VT, X, | ||
DAG.getNOT( | ||
diff -ruN --strip-trailing-cr a/llvm/test/CodeGen/X86/pr108731.ll b/llvm/test/CodeGen/X86/pr108731.ll | ||
--- a/llvm/test/CodeGen/X86/pr108731.ll | ||
+++ b/llvm/test/CodeGen/X86/pr108731.ll | ||
@@ -192,3 +192,23 @@ | ||
ret void | ||
} | ||
|
||
+define void @PR113240(i64 %a) { | ||
+; CHECK-LABEL: PR113240: | ||
+; CHECK: # %bb.0: # %entry | ||
+; CHECK-NEXT: movq %rdi, %rax | ||
+; CHECK-NEXT: notq %rax | ||
+; CHECK-NEXT: movabsq $8796093022206, %rcx # imm = 0x7FFFFFFFFFE | ||
+; CHECK-NEXT: notq %rcx | ||
+; CHECK-NEXT: orq %rax, %rcx | ||
+; CHECK-NEXT: andq %rdi, %rcx | ||
+; CHECK-NEXT: movq %rcx, 0 | ||
+; CHECK-NEXT: retq | ||
+entry: | ||
+ %and = and i64 %a, 8796093022206 | ||
+ %bf.value = and i64 8796093022206, 0 | ||
+ %not = xor i64 %and, -1 | ||
+ %and4 = and i64 %a, %not | ||
+ store i64 %and4, ptr null, align 8 | ||
+ ret void | ||
+} | ||
+ |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,47 @@ | ||
|
||
--- a/lib/Conversion/TritonToTritonGPU/TritonGPUConversion.cpp 2024-08-05 02:40:13.000000000 -0700 | ||
+++ b/lib/Conversion/TritonToTritonGPU/TritonGPUConversion.cpp 2024-10-24 02:13:18.000000000 -0700 | ||
@@ -56,7 +56,7 @@ | ||
// This will create newArg, and map(origArg, newArg) | ||
addArgumentMaterialization([&](OpBuilder &builder, | ||
RankedTensorType tensorType, ValueRange inputs, | ||
- Location loc) -> std::optional<Value> { | ||
+ Location loc) -> Value { | ||
// Allows partial TTIR to TTGIR conversion by materializing a conversion for | ||
// remaining arguments that have been converted to a new type. | ||
// We use this to rewrite triton_gpu.sparse_dot in a separate pass after | ||
@@ -65,14 +65,14 @@ | ||
inputs); | ||
llvm_unreachable("Argument rematerialization should not happen in Triton " | ||
"-> TritonGPU conversion"); | ||
- return std::nullopt; | ||
+ return Value(); | ||
}); | ||
|
||
// If the origValue still has live user(s), use this to | ||
// convert origValue to newValue | ||
addSourceMaterialization([&](OpBuilder &builder, RankedTensorType tensorType, | ||
ValueRange inputs, | ||
- Location loc) -> std::optional<Value> { | ||
+ Location loc) -> Value { | ||
// Allows partial TTIR to TTGIR conversion by materializing a conversion for | ||
// remaining uses of values that have been converted to a new type. | ||
// We use this to rewrite triton_gpu.sparse_dot in a separate pass after | ||
@@ -81,7 +81,7 @@ | ||
inputs); | ||
llvm_unreachable("Source rematerialization should not happen in Triton -> " | ||
"TritonGPU Conversion"); | ||
- return std::nullopt; | ||
+ return Value(); | ||
}); | ||
|
||
// This will be called when (desiredType != newOperandType) | ||
@@ -91,7 +91,7 @@ | ||
ValueRange inputs, Location loc) { | ||
auto cast = | ||
builder.create<triton::gpu::ConvertLayoutOp>(loc, tensorType, inputs); | ||
- return std::optional<Value>(cast.getResult()); | ||
+ return Value(cast.getResult()); | ||
}); | ||
} | ||
|
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,43 +1 @@ | ||
Auto generated patch. Do not edit or delete it, even if empty. | ||
diff -ruN --strip-trailing-cr a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
@@ -50049,8 +50049,9 @@ | ||
SDValue X, Y, Z; | ||
if (sd_match(N, m_And(m_Value(X), | ||
m_OneUse(m_Or(m_Value(Y), m_Not(m_Value(Z))))))) { | ||
- // Don't fold if Y is a constant to prevent infinite loops. | ||
- if (!isa<ConstantSDNode>(Y)) | ||
+ // Don't fold if Y or Z are constants to prevent infinite loops. | ||
+ if (!DAG.isConstantIntBuildVectorOrConstantInt(Y) && | ||
+ !DAG.isConstantIntBuildVectorOrConstantInt(Z)) | ||
return DAG.getNode( | ||
ISD::AND, DL, VT, X, | ||
DAG.getNOT( | ||
diff -ruN --strip-trailing-cr a/llvm/test/CodeGen/X86/pr108731.ll b/llvm/test/CodeGen/X86/pr108731.ll | ||
--- a/llvm/test/CodeGen/X86/pr108731.ll | ||
+++ b/llvm/test/CodeGen/X86/pr108731.ll | ||
@@ -192,3 +192,23 @@ | ||
ret void | ||
} | ||
|
||
+define void @PR113240(i64 %a) { | ||
+; CHECK-LABEL: PR113240: | ||
+; CHECK: # %bb.0: # %entry | ||
+; CHECK-NEXT: movq %rdi, %rax | ||
+; CHECK-NEXT: notq %rax | ||
+; CHECK-NEXT: movabsq $8796093022206, %rcx # imm = 0x7FFFFFFFFFE | ||
+; CHECK-NEXT: notq %rcx | ||
+; CHECK-NEXT: orq %rax, %rcx | ||
+; CHECK-NEXT: andq %rdi, %rcx | ||
+; CHECK-NEXT: movq %rcx, 0 | ||
+; CHECK-NEXT: retq | ||
+entry: | ||
+ %and = and i64 %a, 8796093022206 | ||
+ %bf.value = and i64 8796093022206, 0 | ||
+ %not = xor i64 %and, -1 | ||
+ %and4 = and i64 %a, %not | ||
+ store i64 %and4, ptr null, align 8 | ||
+ ret void | ||
+} | ||
+ |
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