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[HW/SW] Cheshire integration - Linux on FPGA #2405

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[HW/SW] Cheshire integration - Linux on FPGA

[HW/SW] Cheshire integration - Linux on FPGA #2405

Run time

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Job Run time
check-trailing-whitespaces
6s
tc-gcc
45s
tc-isa-sim
32s
check-license
27s
tc-llvm
1m 19s
tc-verilator
13s
compile-ara (2_lanes)
2m 57s
compile-ara (4_lanes)
2m 58s
compile-ara (8_lanes)
3m 4s
compile-ara (16_lanes)
3m 19s
check-clang-format
1m 19s
compile-riscv-tests (2_lanes)
2m 46s
compile-apps (2_lanes)
1m 7s
compile-riscv-tests (4_lanes)
1m 13s
compile-apps (4_lanes)
1m 8s
compile-riscv-tests (8_lanes)
1m 6s
compile-apps (8_lanes)
1m 8s
compile-riscv-tests (16_lanes)
2m 31s
compile-apps (16_lanes)
1m 11s
riscv-tests-spike
1m 18s
simulate (hello_world, 2_lanes)
35s
riscv-tests-simv (2_lanes)
9m 45s
simulate (hello_world, 4_lanes)
16s
benchmark (2_lanes)
47m 36s
riscv-tests-simv (4_lanes)
20m 25s
simulate (hello_world, 8_lanes)
17s
benchmark (4_lanes)
45m 50s
riscv-tests-simv (8_lanes)
40m 8s
simulate (hello_world, 16_lanes)
18s
benchmark (8_lanes)
45m 9s
riscv-tests-simv (16_lanes)
1h 34m 23s
simulate (imatmul, 2_lanes)
8m 21s
benchmark (16_lanes)
54m 10s
simulate (imatmul, 4_lanes)
7m 57s
simulate (imatmul, 8_lanes)
9m 9s
simulate (imatmul, 16_lanes)
12m 23s
simulate (fmatmul, 2_lanes)
9m 6s
simulate (fmatmul, 4_lanes)
9m 19s
simulate (fmatmul, 8_lanes)
11m 17s
simulate (fmatmul, 16_lanes)
16m 20s
simulate (iconv2d, 2_lanes)
2m 49s
simulate (iconv2d, 4_lanes)
3m 16s
simulate (iconv2d, 8_lanes)
3m 52s
simulate (iconv2d, 16_lanes)
5m 53s
simulate (fconv2d, 2_lanes)
3m 44s
simulate (fconv2d, 4_lanes)
4m 10s
simulate (fconv2d, 8_lanes)
5m 11s
simulate (fconv2d, 16_lanes)
8m 27s
simulate (fconv3d, 2_lanes)
6m 59s
simulate (fconv3d, 4_lanes)
7m 9s
simulate (fconv3d, 8_lanes)
8m 10s
simulate (fconv3d, 16_lanes)
11m 27s
simulate (jacobi2d, 2_lanes)
8m 43s
simulate (jacobi2d, 4_lanes)
13m 9s
simulate (jacobi2d, 8_lanes)
21m 42s
simulate (jacobi2d, 16_lanes)
38m 48s
simulate (dropout, 2_lanes)
41s
simulate (dropout, 4_lanes)
32s
simulate (dropout, 8_lanes)
45s
simulate (dropout, 16_lanes)
1m 8s
simulate (fft, 2_lanes)
28s
simulate (fft, 4_lanes)
54s
simulate (fft, 8_lanes)
52s
simulate (fft, 16_lanes)
1m 22s
simulate (dwt, 2_lanes)
41s
simulate (dwt, 4_lanes)
35s
simulate (dwt, 8_lanes)
47s
simulate (dwt, 16_lanes)
1m 11s
simulate (exp, 2_lanes)
35s
simulate (exp, 4_lanes)
27s
simulate (exp, 8_lanes)
29s
simulate (exp, 16_lanes)
55s
simulate (softmax, 2_lanes)
1m 2s
simulate (softmax, 4_lanes)
1m 26s
simulate (softmax, 8_lanes)
2m 14s
simulate (softmax, 16_lanes)
3m 42s
simulate (dotproduct, 2_lanes)
23s
simulate (dotproduct, 4_lanes)
47s
simulate (dotproduct, 8_lanes)
40s
simulate (dotproduct, 16_lanes)
59s
simulate (fdotproduct, 2_lanes)
23s
simulate (fdotproduct, 4_lanes)
29s
simulate (fdotproduct, 8_lanes)
43s
simulate (fdotproduct, 16_lanes)
59s
simulate (pathfinder, 2_lanes)
9m 15s
simulate (pathfinder, 4_lanes)
13m 52s
simulate (pathfinder, 8_lanes)
22m 1s
simulate (pathfinder, 16_lanes)
37m 23s
simulate (roi_align, 2_lanes)
18s
simulate (roi_align, 4_lanes)
17s
simulate (roi_align, 8_lanes)
18s
simulate (roi_align, 16_lanes)
35s
roofline
1m 36s
clean-up
3s
clean-up-compile-runs (2_lanes)
5s
clean-up-compile-runs (4_lanes)
3s
clean-up-compile-runs (8_lanes)
8s
clean-up-compile-runs (16_lanes)
4s
12h 18m 47s