[HW/SW] Cheshire integration - Linux on FPGA #2410
Triggered via pull request
October 19, 2024 15:15
Status
Success
Total duration
6h 11m 38s
Artifacts
19
ci.yml
on: pull_request
tc-llvm
1m 30s
tc-isa-sim
38s
tc-verilator
16s
tc-gcc
43s
check-license
26s
check-trailing-whitespaces
6s
Matrix: compile-apps
check-clang-format
57s
Matrix: compile-ara
Matrix: compile-riscv-tests
Matrix: simulate
Matrix: benchmark
Matrix: riscv-tests-simv
Annotations
11 warnings
Artifacts
Produced during runtime
Name | Size | |
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dotproduct_plots
|
640 KB |
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dotproducts-16_lanes
|
658 Bytes |
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dotproducts-2_lanes
|
657 Bytes |
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dotproducts-4_lanes
|
671 Bytes |
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dotproducts-8_lanes
|
668 Bytes |
|
dropout_roofline
|
6.8 KB |
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dwt_roofline
|
6.63 KB |
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exp_roofline
|
6.75 KB |
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fconv2d_roofline
|
8.05 KB |
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fconv3d_roofline
|
8.63 KB |
|
fdotproduct_plots
|
640 KB |
|
fft_roofline
|
6.22 KB |
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fmatmul_roofline
|
8.31 KB |
|
iconv2d_roofline
|
8.01 KB |
|
imatmul_roofline
|
7.83 KB |
|
jacobi2d_roofline
|
6.96 KB |
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pathfinder_roofline
|
6.56 KB |
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roi_align_roofline
|
6.15 KB |
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softmax_roofline
|
6.8 KB |
|