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[hardware] Clean-up unused clk-gating cell
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mp-17 committed Sep 8, 2023
1 parent c53eff4 commit ec0e379
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Showing 3 changed files with 1 addition and 25 deletions.
1 change: 0 additions & 1 deletion Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@ sources:
- hardware/src/lane/simd_mul.sv
- hardware/src/lane/vector_regfile.sv
- hardware/src/lane/power_gating_generic.sv
- hardware/src/lane/clk_gating_generic.sv
- hardware/src/masku/masku.sv
- hardware/src/sldu/p2_stride_gen.sv
- hardware/src/sldu/sldu_op_dp.sv
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18 changes: 0 additions & 18 deletions hardware/src/lane/clk_gating_generic.sv

This file was deleted.

7 changes: 1 addition & 6 deletions hardware/src/lane/vmfpu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -287,12 +287,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
// Clock-gate for the multipliers
logic clkgate_en_d, clkgate_en_q, clk_i_gated;

`ifdef GF22
clk_gating_gf22
`else
tc_clk_gating
`endif
i_simd_mul_manual_clk_gate (
tc_clk_gating i_simd_mul_manual_clk_gate (
.clk_i (clk_i ),
.en_i (clkgate_en_q),
.test_en_i (1'b0 ),
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