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Extend backreferencing #323

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11 changes: 10 additions & 1 deletion cheshire/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,8 @@ ARA_ROOT := $(MAKEFILE_DIR)/..
BACKREF_CHS_ROOT ?= $(realpath ../../../../..)
BACKREF_CHS_XIL_SCRIPTS := $(BACKREF_CHS_ROOT)/target/xilinx/scripts

# Tools
VIVADO ?= 'vitis-2020.2 vivado'

# Set up Bender targets and defines
# default configuration for Cheshire + Ara is 2_lanes
Expand All @@ -20,11 +22,18 @@ include $(ARA_ROOT)/config/$(ARA_CONFIGURATION).mk
BOARD := vcu128
CUSTOM_BENDER_TARGETS := -t fpga -t cv64a6_imafdcv_sv39 -t cva6 -t $(BOARD) --define ARA --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen)

.PHONY: ara-chs-xilinx-$(BOARD) update_xilinx_src clean
.PHONY: ara-chs-xilinx-$(BOARD) ara-chs-flash-$(BOARD) apply-patches update_xilinx_src clean

ara-chs-xilinx-$(BOARD): update_xilinx_src
make -C $(BACKREF_CHS_ROOT) chs-xilinx-$(BOARD)

ara-chs-flash-$(BOARD):
make -C $(BACKREF_CHS_ROOT) chs-xilinx-flash-$(BOARD) VIVADO=$(VIVADO)

apply-patches:
cd $(BACKREF_CHS_ROOT) && \
git apply $(ARA_ROOT)/cheshire/patches/device_tree.patch

update_xilinx_src:
cd $(BACKREF_CHS_ROOT) && \
bender script vivado $(CUSTOM_BENDER_TARGETS) > $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.vcu128.tcl
Expand Down
13 changes: 13 additions & 0 deletions cheshire/patches/device_tree.patch
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
diff --git a/sw/boot/cheshire.dtsi b/sw/boot/cheshire.dtsi
index 76decc8..5561e87 100644
--- a/sw/boot/cheshire.dtsi
+++ b/sw/boot/cheshire.dtsi
@@ -30,7 +30,7 @@
status = "okay";
compatible = "eth,ariane", "riscv";
clock-frequency = <50000000>; // 50 MHz
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdcv";
mmu-type = "riscv,sv39";
tlb-split;
reg = <0>;
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