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Add loop-unrolling debug rewrite for SystemVerilog (#744)
* Add loop-unrolling debug rewrite for SystemVerilog It can be useful for debug of SystemVerilog generation. Loops being a relevant source of issues in the generation, being able to replace loops with their expanded equivalent helps us determine whether an issue is related to loops or not. * Format with ocamlformat 0.26.0 * Replace print_endline with Reporting.warn for warning * Add option to override warning supression on rewrites --------- Co-authored-by: Nicolas Phan <nicolas.phan@codasip.com>
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