formating fix

riscv-non-isa · Nov 15, 2023 · fd34f1e · fd34f1e
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diff --git a/server_soc_tests.adoc b/server_soc_tests.adoc
@@ -3,7 +3,7 @@
 === RISC-V Harts
 
 [width=100%]
-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#            ^| Requirement
 | ME_RVA_010_010 a| For each application processor hart:
@@ -61,7 +61,7 @@
 === Clocks and Timers
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#            ^| Requirement
 | ME_CTI_010_010 a| Parse ACPI RHCT table to determine the time base frequency
@@ -72,7 +72,7 @@
 === External Interrupt Controllers
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#            ^| Requirement
 | ME_IIC_010_010 a| For each application processor hart:
@@ -139,7 +139,7 @@
 === Input-Output Memory Management Unit (IOMMU)
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#            ^| Requirement
 | ME_IOM_010_010 a| * Locate all IOMMUs reported by APCI and verify they are of
@@ -228,7 +228,7 @@
 ==== Enhanced Configuration Access Method (ECAM)
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#        ^| Requirement
 | MF_ECM_010 a| * Parse ACPI MCFG tables to local all ECAM ranges.
@@ -329,7 +329,7 @@ The ECAM address ranges MUST have the following physical memory
 ==== PCIe Memory Space
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | MMS_010  | The SoC MUST support designating, for each hierarchy domain, one or
@@ -426,7 +426,7 @@ These controls may be applicable to the root complex, switches, multi-function
 devices, and SR-IOV capable devices.
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | ACS_010 a| PCIe root ports and SoC integrated downstream switch ports MUST
@@ -475,7 +475,7 @@ address of a host memory location or the address of a location in the memory
 space of a peer endpoint or RCiEP.
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | ADR_010  | The host bridge MUST request IOMMU translations for addresses
@@ -545,7 +545,7 @@ are routed by ID. Such requests may be ID Configuration requests, ID routed
 messages or completions.
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | IDR_010  | Configuration requests from endpoints and RCiEP MUST be treated as
@@ -565,7 +565,7 @@ messages or completions.
 ==== Cacheability and Coherence
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | CCS_010  | The host bridge MUST enforce PCIe memory ordering rules and SHOULD
@@ -635,7 +635,7 @@ messages or completions.
 A message signaled interrupt (MSI or MSI-X) is the preferred interrupt signaling
 mechanism in PCIe.
 
-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | MSI_010  | Message Signaled Interrupts MUST be supported.
@@ -656,7 +656,7 @@ mechanism in PCIe.
 ==== Precision Time Measurement (PTM)
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | PTM_010  | PCIe root ports MAY support PCIe PTM capability.
@@ -683,7 +683,7 @@ mechanism in PCIe.
 ==== Error and Event Reporting
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | AER_010  | PCIe root ports MUST support advanced error reporting (AER)
@@ -719,7 +719,7 @@ mechanism in PCIe.
 
 ==== Vendor Specific Registers
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | VSR_010 a| Vendors specific registers in the root ports, host bridge, RCiEP,
@@ -749,7 +749,7 @@ mechanism in PCIe.
 ==== SoC-Integrated PCIe Devices
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | SID_010  | SoC-integrated PCIe devices MUST implement all software visible
@@ -813,7 +813,7 @@ mechanism in PCIe.
 === Reliability, Availability, and Serviceability (RAS)
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | RAS_010  | The level of RAS implemented by the SoC is `UNSPECIFIED`.
@@ -958,7 +958,7 @@ as cache capacity, memory bandwidth, interconnect bandwidth, power consumption,
 and more.
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | QOS_010  | The SoC SHOULD incorporate QoS mechanisms to mitigate unwarranted
@@ -1061,7 +1061,7 @@ seamlessly integrate into the server management frameworks and tools employed by
 data centers and enterprises.
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | MNG_010  | The SoC SHOULD incorporate support for an x1 PCIe lane, preferably
@@ -1107,7 +1107,7 @@ data centers and enterprises.
 === Debug
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | DBG_010  | The SoC MUST support at least one RISC-V debug module as specified
@@ -1141,7 +1141,7 @@ data centers and enterprises.
 
 === Trace
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | TRC_010  | The SoC MUST support either the RISC-V E-trace cite:[ETRACE] or the
@@ -1166,7 +1166,7 @@ data centers and enterprises.
 === Performance Monitoring
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | SPM_010 a| Significant caches within the SoC SHOULD incorporate an HPM capable
@@ -1215,7 +1215,7 @@ data centers and enterprises.
 === Security Requirements
 
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-[%header, cols="5,25"]
+[%header, cols="8,25"]
 |===
 | ID#     ^| Requirement
 | SEC_010  | The PCIe root ports within the SoC SHOULD support PCIe Integrity and

diff --git a/server_soc_ts_header.adoc b/server_soc_ts_header.adoc
@@ -34,7 +34,7 @@ endif::[]
 :footnote:
 :xrefstyle: short
 
-= RISC-V Server SoC Specification
+= RISC-V Server SoC Test Specification
 Server SoC Task Group
 
 // Preamble

diff --git a/server_soc_ts_intro.adoc b/server_soc_ts_intro.adoc
@@ -22,10 +22,10 @@ tests.
 The tests in this specification are documented use the following format:
 
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-[%header, cols="5,5,20"]
+[%header, cols="8,20"]
 |===
 | TEST_ID#       ^| Test algorithm
-| AB_CAT_NNN_MMM  | The `CAT_NNN` identifies a requirement in the RISC-V Server
+| AB_CAT_NNN_MMM a| The `CAT_NNN` identifies a requirement in the RISC-V Server
                     SoC specification. Each requirement is associated with one
                     or more tests identified by `MMM`. The test IDs are prefixed
                     with two character prefix - `AB`.                          +