Merge pull request #54 from riscv-software-src/patch-canary

Patch canary

.github/workflows/test.yml

@@ -37,6 +37,24 @@ jobs:
         run: riscv_ctg -r -d rv32i -bi rv32i -cf sample_cgfs/dataset.cgf -cf sample_cgfs/rv32i.cgf -v debug -p $(nproc)
 
   check-version:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+
+      - name: version check
+        run: |
+          export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); 
+          echo "CHANGELOG VERSION: $CHNGVER"
+          export INITVER=$(grep -P "__version__ = '.*?'" riscv_ctg/__init__.py | awk '{print $3}'|sed "s/'//g"); 
+          echo "INIT VERSION: $INITVER"
+          if [ "$CHNGVER" = "$INITVER" ]; then
+              echo "Versions are equal in Changelog and init.py."
+          else
+              echo "Versions are not equal in Changelog and init.py."
+              exit 1
+          fi
+
+  check-version-changelog:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2

riscv_ctg/__init__.py

@@ -4,5 +4,5 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = 'incorebot@gmail.com'
-__version__ = '0.10.2'
+__version__ = '0.10.3'
 

riscv_ctg/env/arch_test.h

@@ -92,14 +92,16 @@
     #define FLREG flw
     #define FSREG fsw
     #define FREGWIDTH 4
-    #if XLEN==64
-        #define SIGALIGN 8
-    #else
-        #define SIGALIGN 4
-    #endif
   #endif
 #endif
 
+#if FLEN>XLEN
+    #define SIGALIGN FREGWIDTH
+#else
+    #define SIGALIGN REGWIDTH
+#endif
+
+
 #if SIGALIGN==8
   #define CANARY \
       .dword 0x6F5CA309E7D4B281

setup.cfg

@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.10.2
+current_version = 0.10.3
 commit = True
 tag = True
 

setup.py

@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_ctg',
-    version='0.10.2',
+    version='0.10.3',
     description="RISC-V CTG",
     long_description=readme + '\n\n',
     classifiers=[