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Rollup of 6 pull requests #114673

Merged
merged 18 commits into from
Aug 10, 2023
Merged

Rollup of 6 pull requests #114673

merged 18 commits into from
Aug 10, 2023

Commits on Aug 2, 2023

  1. test_get_dbpath_for_term(): Use assert_eq!()

    For better failure messages.
    Enselic committed Aug 2, 2023
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Commits on Aug 4, 2023

  1. Detect method not found on arbitrary self type with different mutability

    ```
    error[E0599]: no method named `x` found for struct `Pin<&S>` in the current scope
      --> $DIR/arbitrary_self_type_mut_difference.rs:11:18
       |
    LL |     Pin::new(&S).x();
       |                  ^ help: there is a method with a similar name: `y`
       |
    note: method is available for `Pin<&mut S>`
      --> $DIR/arbitrary_self_type_mut_difference.rs:6:5
       |
    LL |     fn x(self: Pin<&mut Self>) {}
       |     ^^^^^^^^^^^^^^^^^^^^^^^^^^
    ```
    
    Related to rust-lang#57994, as one of the presented cases can lead to code like
    this.
    estebank committed Aug 4, 2023
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  2. Add tests for rust-lang#57994

    estebank committed Aug 4, 2023
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Commits on Aug 9, 2023

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  2. feat: riscv-interrupt-{m,s} calling conventions

    Similar to prior support added for the mips430, avr, and x86 targets
    this change implements the rough equivalent of clang's
    [`__attribute__((interrupt))`][clang-attr] for riscv targets, enabling
    e.g.
    
    ```rust
    static mut CNT: usize = 0;
    
    pub extern "riscv-interrupt-m" fn isr_m() {
        unsafe {
            CNT += 1;
        }
    }
    ```
    
    to produce highly effective assembly like:
    
    ```asm
    pub extern "riscv-interrupt-m" fn isr_m() {
    420003a0:       1141                    addi    sp,sp,-16
        unsafe {
            CNT += 1;
    420003a2:       c62a                    sw      a0,12(sp)
    420003a4:       c42e                    sw      a1,8(sp)
    420003a6:       3fc80537                lui     a0,0x3fc80
    420003aa:       63c52583                lw      a1,1596(a0) # 3fc8063c <_ZN12esp_riscv_rt3CNT17hcec3e3a214887d53E.0>
    420003ae:       0585                    addi    a1,a1,1
    420003b0:       62b52e23                sw      a1,1596(a0)
        }
    }
    420003b4:       4532                    lw      a0,12(sp)
    420003b6:       45a2                    lw      a1,8(sp)
    420003b8:       0141                    addi    sp,sp,16
    420003ba:       30200073                mret
    ```
    
    (disassembly via `riscv64-unknown-elf-objdump -C -S --disassemble ./esp32c3-hal/target/riscv32imc-unknown-none-elf/release/examples/gpio_interrupt`)
    
    This outcome is superior to hand-coded interrupt routines which, lacking
    visibility into any non-assembly body of the interrupt handler, have to
    be very conservative and save the [entire CPU state to the stack
    frame][full-frame-save]. By instead asking LLVM to only save the
    registers that it uses, we defer the decision to the tool with the best
    context: it can more accurately account for the cost of spills if it
    knows that every additional register used is already at the cost of an
    implicit spill.
    
    At the LLVM level, this is apparently [implemented by] marking every
    register as "[callee-save]," matching the semantics of an interrupt
    handler nicely (it has to leave the CPU state just as it found it after
    its `{m|s}ret`).
    
    This approach is not suitable for every interrupt handler, as it makes
    no attempt to e.g. save the state in a user-accessible stack frame. For
    a full discussion of those challenges and tradeoffs, please refer to
    [the interrupt calling conventions RFC][rfc].
    
    Inside rustc, this implementation differs from prior art because LLVM
    does not expose the "all-saved" function flavor as a calling convention
    directly, instead preferring to use an attribute that allows for
    differentiating between "machine-mode" and "superivsor-mode" interrupts.
    
    Finally, some effort has been made to guide those who may not yet be
    aware of the differences between machine-mode and supervisor-mode
    interrupts as to why no `riscv-interrupt` calling convention is exposed
    through rustc, and similarly for why `riscv-interrupt-u` makes no
    appearance (as it would complicate future LLVM upgrades).
    
    [clang-attr]: https://clang.llvm.org/docs/AttributeReference.html#interrupt-risc-v
    [full-frame-save]: https://github.com/esp-rs/esp-riscv-rt/blob/9281af2ecffe13e40992917316f36920c26acaf3/src/lib.rs#L440-L469
    [implemented by]: https://github.com/llvm/llvm-project/blob/b7fb2a3fec7c187d58a6d338ab512d9173bca987/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L61-L67
    [callee-save]: https://github.com/llvm/llvm-project/blob/973f1fe7a8591c7af148e573491ab68cc15b6ecf/llvm/lib/Target/RISCV/RISCVCallingConv.td#L30-L37
    [rfc]: rust-lang/rfcs#3246
    sethp committed Aug 9, 2023
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  3. fix: add RiscvInterrupt* cconv to smir

    These new interrupt calling conventions are not themselves stabilized,
    but there are other unstable calling conventions present in the SMIR
    mapping (e.g. AVR interrupts) and the mapping appears to be "complete"
    so far, with no obvious way to represent unstable conventions separately
    from the stable ones.
    sethp committed Aug 9, 2023
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  4. fix(test): improve sensitivity of hygene tests

    The change in 07f855d introduced a
    trailing numeral of some kind after the `extern crate
    compiler_builtins`, which appears to have caused at least two false
    negatives (654b924 and 657fd24). Instead, this change normalizes the
    test output to ignore the number (of symbols rustc recognizes?) to avoid
    needing to re-`--bless` these two tests for unrelated changes.
    sethp committed Aug 9, 2023
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  5. review comments

    estebank committed Aug 9, 2023
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  9. Rollup merge of rust-lang#110435 - aDotInTheVoid:rdj-field-ordering, …

    …r=GuillaumeGomez
    
    rustdoc-json: Add test for field ordering.
    
    Inspired by [this on twitter](https://twitter.com/PredragGruevski/status/1647705616650043392), the ordering of fields really matters, so we should test we preserve it through json.
    
    r? rustdoc
    matthiaskrgr authored Aug 9, 2023
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  10. Rollup merge of rust-lang#111891 - rustbox:feat/riscv-isr-cconv, r=ja…

    …ckh726
    
    feat: `riscv-interrupt-{m,s}` calling conventions
    
    Similar to prior support added for the mips430, avr, and x86 targets this change implements the rough equivalent of clang's [`__attribute__((interrupt))`][clang-attr] for riscv targets, enabling e.g.
    
    ```rust
    static mut CNT: usize = 0;
    
    pub extern "riscv-interrupt-m" fn isr_m() {
        unsafe {
            CNT += 1;
        }
    }
    ```
    
    to produce highly effective assembly like:
    
    ```asm
    pub extern "riscv-interrupt-m" fn isr_m() {
    420003a0:       1141                    addi    sp,sp,-16
        unsafe {
            CNT += 1;
    420003a2:       c62a                    sw      a0,12(sp)
    420003a4:       c42e                    sw      a1,8(sp)
    420003a6:       3fc80537                lui     a0,0x3fc80
    420003aa:       63c52583                lw      a1,1596(a0) # 3fc8063c <_ZN12esp_riscv_rt3CNT17hcec3e3a214887d53E.0>
    420003ae:       0585                    addi    a1,a1,1
    420003b0:       62b52e23                sw      a1,1596(a0)
        }
    }
    420003b4:       4532                    lw      a0,12(sp)
    420003b6:       45a2                    lw      a1,8(sp)
    420003b8:       0141                    addi    sp,sp,16
    420003ba:       30200073                mret
    ```
    
    (disassembly via `riscv64-unknown-elf-objdump -C -S --disassemble ./esp32c3-hal/target/riscv32imc-unknown-none-elf/release/examples/gpio_interrupt`)
    
    This outcome is superior to hand-coded interrupt routines which, lacking visibility into any non-assembly body of the interrupt handler, have to be very conservative and save the [entire CPU state to the stack frame][full-frame-save]. By instead asking LLVM to only save the registers that it uses, we defer the decision to the tool with the best context: it can more accurately account for the cost of spills if it knows that every additional register used is already at the cost of an implicit spill.
    
    At the LLVM level, this is apparently [implemented by] marking every register as "[callee-save]," matching the semantics of an interrupt handler nicely (it has to leave the CPU state just as it found it after its `{m|s}ret`).
    
    This approach is not suitable for every interrupt handler, as it makes no attempt to e.g. save the state in a user-accessible stack frame. For a full discussion of those challenges and tradeoffs, please refer to [the interrupt calling conventions RFC][rfc].
    
    Inside rustc, this implementation differs from prior art because LLVM does not expose the "all-saved" function flavor as a calling convention directly, instead preferring to use an attribute that allows for differentiating between "machine-mode" and "superivsor-mode" interrupts.
    
    Finally, some effort has been made to guide those who may not yet be aware of the differences between machine-mode and supervisor-mode interrupts as to why no `riscv-interrupt` calling convention is exposed through rustc, and similarly for why `riscv-interrupt-u` makes no appearance (as it would complicate future LLVM upgrades).
    
    [clang-attr]: https://clang.llvm.org/docs/AttributeReference.html#interrupt-risc-v
    [full-frame-save]: https://github.com/esp-rs/esp-riscv-rt/blob/9281af2ecffe13e40992917316f36920c26acaf3/src/lib.rs#L440-L469
    [implemented by]: https://github.com/llvm/llvm-project/blob/b7fb2a3fec7c187d58a6d338ab512d9173bca987/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L61-L67
    [callee-save]: https://github.com/llvm/llvm-project/blob/973f1fe7a8591c7af148e573491ab68cc15b6ecf/llvm/lib/Target/RISCV/RISCVCallingConv.td#L30-L37
    [rfc]: rust-lang/rfcs#3246
    matthiaskrgr authored Aug 9, 2023
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  11. Rollup merge of rust-lang#114377 - Enselic:test_get_dbpath_for_term-u…

    …tf-8, r=thomcc
    
    test_get_dbpath_for_term(): handle non-utf8 paths (fix FIXME)
    
    Removes a FIXME for rust-lang#9639
    
    Part of rust-lang#44366 which is E-help-wanted
    
    The remaining two FIXMEs for rust-lang#9639 are considerably more complicated, so I will create separate PRs for them.
    matthiaskrgr authored Aug 9, 2023
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  12. Rollup merge of rust-lang#114469 - estebank:arbitrary-self-types-mut-…

    …diff, r=davidtwco
    
    Detect method not found on arbitrary self type with different mutability
    
    ```
    error[E0599]: no method named `x` found for struct `Pin<&S>` in the current scope
      --> $DIR/arbitrary_self_type_mut_difference.rs:11:18
       |
    LL |     Pin::new(&S).x();
       |                  ^ help: there is a method with a similar name: `y`
       |
    note: method is available for `Pin<&mut S>`
      --> $DIR/arbitrary_self_type_mut_difference.rs:6:5
       |
    LL |     fn x(self: Pin<&mut Self>) {}
       |     ^^^^^^^^^^^^^^^^^^^^^^^^^^
    ```
    
    Related to rust-lang#57994, as one of the presented cases can lead to code like this.
    matthiaskrgr authored Aug 9, 2023
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  13. Rollup merge of rust-lang#114587 - ouz-a:smir_allocation, r=oli-obk

    Convert Const to Allocation in smir
    
    Continuation of previous pr rust-lang#114466
    
    cc rust-lang/project-stable-mir#15
    
    r? `@oli-obk`
    matthiaskrgr authored Aug 9, 2023
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  14. Rollup merge of rust-lang#114670 - compiler-errors:issue-114660, r=cj…

    …gillot
    
    Don't use `type_of` to determine if item has intrinsic shim
    
    When we're calling `resolve_instance` on an inline const, we were previously looking at the `type_of` for that const, seeing that it was an `extern "intrinsic"` fn def, and treating it as if we were computing the instance of that intrinsic itself. This is incorrect.
    
    Instead, we should be using the def-id of the item we're computing to determine if it's an intrinsic.
    
    Fixes rust-lang#114660
    matthiaskrgr authored Aug 9, 2023
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