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Streaming composition
In many numerical applications, computations may involve 2 or more BLAS call. In FBLAS, each of the HLS Module implementing a numerical routine is characterized by a streaming interface, which is used to receive input data and to produce results. The streaming interface introduced in enables modules to communicate through on-chip memory, rather than through off-chip DRAM. This has different advantages:
- it reduces costly off-chip memory accesses, as data is streamed directly by the producer module to the consumer module, rather than storing and loading it to DRAM;
- it allows pipeline parallel execution of different modules that are configured simultaneously on the FPGA;
- limit the host intervention, as module computation is initiated by data arriving from another module.
In the following, we will describe basic composition rule that will help programmer in enforce validity of a module composition obtained with the HLS Modules generator.
A numerical computation implemented with FBLAS can be seen as a module directed acyclic graph (MDAG), in which vertices are hardware modules, and edges represent data streamed between modules. Source and sink vertices are interface modules, that are responsible for off-chip (device RAM) memory accesses.
Each HLS module interface, is defined by the number of elements consumed and produced at its inputs and outputs, together with information about supported tiling schema (all this information are currently available in the Module documentation, in doxygen format, and in the wikipage Streaming Interface).
We consider an MDAG to be valid if it expresses a composition that will terminate, i.e., it does not stall forever, i.e. the module is not blocked because its output channel is full or an input channel is empty.
Additionally, an edge in the MDAG between module A
and B
is valid if:
- the number of elements produced is identical to the number of elements consumed; and
- the order in which elements are consumed corresponds to order in which they are produced.