Improve idle power (#62)

* elcipse settings

* change buck voltage 12v -> 10v for efficiency

* improve comments

* introduce R33.3 shunt scaling factor

* experimental clock divider (not working yet!)

* fix endpoint

firmware/.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1663133287212116391" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1640006224415175060" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

firmware/src/adc/adc.c

@@ -193,14 +193,14 @@ void ADC_DTSE_Init(void)
     // Setup DTSE Sequence Trigger - See "DTSE Trigger Mapping Table" in the PAC55XX Family User's Guide
     //========================================================================================================
 
-	//  Timer A CCR2 = Trigger 0 and will initiate Sequence starting at Entry 0
+	//  Timer A CCR2 = Trigger 0 and initiate sequence starting at DTSE Entry 0
     PAC55XX_ADC->DTSETRIGENT0TO3.FORCE0 = 0;                            // Reset to 0
     PAC55XX_ADC->DTSETRIGENT0TO3.TRIG0CFGIDX = 0;                       // DTSE Trigger 0 Sequence Configuration Entry Index
     PAC55XX_ADC->DTSETRIGENT0TO3.TRIG0EDGE = ADCDTSE_TRIGEDGE_RISING;   // PWMA0 rising edge
 
     pac5xxx_timer_a_ccctr0_value_set(1);
 
-    //===== Setup DTSE Sequence A (zerocrossing) - Starts at Entry 0 =====
+    //===== Setup DTSE Sequence A (sense offset) - Starts at Entry 0 =====
     pac5xxx_dtse_seq_config(0, ADC0, EMUX_AB10 , 0,           0);
     pac5xxx_dtse_seq_config(1, ADC0, EMUX_AB10 , 0,           0);
     pac5xxx_dtse_seq_config(2, ADC0, EMUX_AB13 , 0,           0);       // Get VPTAT result at DTSERES2
@@ -213,14 +213,14 @@ void ADC_DTSE_Init(void)
     pac5xxx_dtse_seq_config(9, ADC0, EMUX_AIO54, 0,           0);
     pac5xxx_dtse_seq_config(10, ADC0, 0        , 0,           SEQ_END); // Get result at DTSERES10
 
-    //  Timer A CCR2 = Trigger 0 and will initiate Sequence starting at Entry 0
+    //  Timer A CCR2 = Trigger 0 and initiate sequence starting at DTSE Entry 0
     PAC55XX_ADC->DTSETRIGENT0TO3.FORCE1 = 0;                            // Reset to 0
     PAC55XX_ADC->DTSETRIGENT0TO3.TRIG1CFGIDX = 12;                      // DTSE Trigger 1 Sequence Configuration Entry Index
     PAC55XX_ADC->DTSETRIGENT0TO3.TRIG1EDGE = ADCDTSE_TRIGEDGE_RISING;   // PWMA0 rising edge
 
     pac5xxx_timer_a_ccctr1_value_set( (ACLK_FREQ_HZ/2/PWM_TIMER_FREQ) - 2);
 
-    //===== Setup DTSE Sequence B (VP crossing) - Starts at Entry 12 =====
+    //===== Setup DTSE Sequence B (sense current) - Starts at Entry 12 =====
     pac5xxx_dtse_seq_config(12, ADC0, EMUX_AIO10, 0,           0);
     pac5xxx_dtse_seq_config(13, ADC0, EMUX_AIO10, 0,           0);
     pac5xxx_dtse_seq_config(14, ADC0, EMUX_AIO32, 0,           0);       // Get result at DTSERES14

firmware/src/adc/adc.h

@@ -48,16 +48,21 @@ typedef enum {
     #define MODULE_MISC_BITS_DEFAULT   ((HIB_BIT_DEFAULT << 7) + (PBEN_BIT_DEFAULT << 6) + (VREFSET_BIT_DEFAULT << 5) + (CLKOUTEN_BIT_DEFAULT << 4) + (MCUALIVE_BIT_DEFAULT << 3) + (TPBD_BIT_DEFAULT << 2) + (RFU_BIT_DEFAULT << 1) + (ENSIG_BIT_DEFAULT << 0))
 #endif
 
+// Current sensing multipler defined as follows:
 // meas * ONE_OVER_ADC_RES * VREF / R * ONE_OVER_ADC_GAIN
-// Examples:
-// 1/2^12 * 3,3 / 0,001 / 32 ~= 0.025176
-//#define SHUNT_SCALING_FACTOR ( 0.025176f )
+
+// Tinymovr R3.3 (alpha2) and later have 2mOhm shunts
+// ^12 * 3.3 / 0.002 / 16 ~= 0.025177
+#define SHUNT_SCALING_FACTOR ( 0.025177f )
+
+// Tinymovr R3.2 (alpha1) and earlier have 1mOhm shunts
 // 1/2^12 * 3,3 / 0,001 / 16 ~= 0.0503
-#define SHUNT_SCALING_FACTOR ( 0.0503f )
-// 1/2^12 * 3,3 / 0,001 / 1 ~= 0.8056
-//#define SHUNT_SCALING_FACTOR ( 0.8056f )
+// #define SHUNT_SCALING_FACTOR ( 0.0503f )
+
+// Inverse of sensing multiplier
 #define ONE_OVER_SHUNT_SCALING_FACTOR ( 1.0f / SHUNT_SCALING_FACTOR )
 
+// VBus scaling factor
 #define VBUS_SCALING_FACTOR ( 0.0127f )
 
 typedef void (*Callback)(void);

firmware/src/config.h

@@ -17,23 +17,35 @@
 
 #define VERSION_MAJOR (0u)
 #define VERSION_MINOR (7u)
-#define VERSION_PATCH (2u)
+#define VERSION_PATCH (3u)
 
 /// TINYMOVR CONFIGURATION OPTIONS ///
 
 // Uncomment to disable live gate driver control
 // #define DRY_RUN
 
-#define ACLK_FREQ_HZ                (300000000)
+// WARNING! PLEASE DO NOT ADJUST CLOCK DIVIDER YET!
+// LEAVE IT AT 1
+// ACLK Clock Divider
+// The ACLK clock is equal to SCLK / ACLK_PRESCALER
+// Higher ACLK_DIVIDER values mean less PWM resolution, but also
+// slightly lower power consumption.
+// Valid values are {1, 2, 3, 4, 5, 6, 7, 8}
+#define ACLK_DIVIDER				(1)
+#define ACLK_FREQ_HZ                (300000000/ACLK_DIVIDER)
 #define HCLK_FREQ_HZ                (150000000)
+
+// PWM Timer Frequency (Hz).
+// Determines the PWM Timer Frequency by varying the
+// PWM timer base.
 #define PWM_TIMER_FREQ              (20000)
 
+// Limits
 #define PWM_LIMIT                   (0.8f)
 #define I_TRIP_MARGIN               (1.25f)
 #define VBUS_LOW_THRESHOLD          (11.0f)
 
-// Calibration
-
+// Calibration timer indices
 #define CAL_R_END_INDEX             (2 * PWM_TIMER_FREQ)
 #define CAL_L_END_INDEX             (3 * PWM_TIMER_FREQ)
 #define CAL_OFFSET_END_INDEX        (4 * PWM_TIMER_FREQ)

firmware/src/system/system.c

@@ -39,7 +39,7 @@ void System_Init(void)
 
     // Configure SCLK=PLLCLK=300 MHz, HCLK=150 MHz, PCLK=150 MHz, ACLK=300 MHz and WaitStates;  Use default PCLKDIV=1
     PAC55XX_SCC->CCSCTL.HCLKDIV = CCSCTL_HCLKDIV_DIV2;          // HCLK = 150 MHz = SCLK/2; when SCLK = PLLCLK
-    PAC55XX_SCC->CCSCTL.ACLKDIV = CCSCTL_ACLKDIV_DIV1;          // ACLK = 300 MHz = SCLK/1; when SCLK = PLLCLK
+    PAC55XX_SCC->CCSCTL.ACLKDIV = (ACLK_DIVIDER - 1);
     PAC55XX_MEMCTL->MEMCTL.WSTATE = 5 + 1;                      // Flash = 150/25 = 6 clocks = 5 WS; So, need 5 + 1 Extra WS
     PAC55XX_SCC->CCSCTL.SCLKMUXSEL = CCSCTL_SCLK_PLLCLK;        // SCLK = PLLCLK
 
@@ -63,6 +63,10 @@ void System_Init(void)
 	// Configure SOC Bridge for talking to CAFE
 	pac5xxx_tile_socbridge_config(1, 0);
 
+	// System Configuration Power Options
+	// Vp = 10V , 440mA-540mA, Charge Pump Enable
+	pac5xxx_tile_register_write(ADDR_SYSCONF, 0x01);
+
 	if (ARM_CM_DWT_CTRL != 0) {        // See if DWT is available
 		ARM_CM_DEMCR      |= 1u << 24;  // Set bit 24
 		ARM_CM_DWT_CYCCNT  = 0;

studio/Python/tinymovr/iface/can/endpoints.py

@@ -191,11 +191,11 @@
     "timings":
     {
         "description": "Get Processor Timings \
-(Busy Cycles/PWM, Total Cycles/PWM)",
+(Total Cycles/PWM, Busy Cycles/PWM)",
         "type": "r",
         "ep_id": 0x01B,
         "types": (DataType.UINT32, DataType.UINT32),
-        "labels": ("busy", "total")
+        "labels": ("total", "busy")
     },
     "save_config":
     {