Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
cpu
mips
vhdl
microprocessor
forwarding
computer-architecture
hazard-detection
risc
dlx
multiplier
branch-predictor
digital-electronics
btb
bht
-
Updated
Dec 10, 2019 - VHDL