A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
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gate-level
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A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
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Jul 4, 2019 - Verilog
Customizable fault-simulation and gate-level editing library for sequential circuits
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Apr 20, 2021 - C
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design
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Jul 29, 2022 - C++
Gate-level circuit model for ROSS
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Feb 20, 2020 - C
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
layouts optimization layout ant-colony-optimization fuzzy-logic optimisation optimisation-algorithms gate-level ant-colony-optimisation electronics-design gate-level-simulation flipflop jkflipflop ant-colony-algorithm powerconsumption cmos-circuits adaptive-fuzzy-logic fuzzy-adaptive optimum-layout layout-design
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May 10, 2022 - MATLAB
End-to-end framework to bridge gate-level hardware stuck-at faults and application-level software degradation in INT8/UINT8 Quantized Neural Networks.
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Jun 5, 2026 - C++
Реализация элементов цифровых схем из базовых логических элементов
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Feb 7, 2021 - VHDL
Area-efficient approximate comparators (4–32 bit) with Verilog RTL, testbenches, and analysis.
verilog synthesis comparator yosys vcd digital-design gate-level rtl-design majority-voting low-power-design hardware-approximation hardware-efficiency gate-substitution gate-merging
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Jun 18, 2025 - Verilog
USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.
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Nov 21, 2024 - Python
Static glitch/hazard analysis: a gate-level netlist + Liberty in, reconvergent-fanout hazards out.
rust asic digital eda semiconductor opendb gate-level physical-design openroad open-source-silicon eda-tools vyges hazard-analysis open-silicon vyges-loom
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Sep 2, 2026 - Rust
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