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ayeshahanifmirza / zero-to-chip-engineer

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Computer Engineering graduate building chip verification skills from scratch — C++, Digital Logic Design, SystemVerilog, RISC-V | Targeting NCDC/NUST Chip Verification Training & M.Sc. FAU Erlangen-Nürnberg, Germany | 2am–5am daily | Kamalia, Pakistan → Germany 🇩🇪

c-plus-plus asic fpga verilog systemverilog computer-architecture icarus-verilog uvm risc-v ncdc semiconductor pakistan functional-verification vlsi-design hdlbits hardware-design chip-verification fau-erlangen
  • Updated Jun 21, 2026

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