reorder-buffer

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bevan-jebanesan / dynamic-instruction-scheduler

Out-of-order processor pipeline simulator with configurable ROB, IQ, and dispatch width

cpp computer-architecture systems-programming microarchitecture processor-simulation out-of-order-execution reorder-buffer

Updated Apr 15, 2026
C++

DramanSalif / instruction-parallelism-and-superscalar-cpu-simualtion

Star

Superscalar CPU simulation models how modern processors execute instructions in parallel and manage hazards, analyzing and scheduling Python function instructions using advanced CPU features.

visualization python education simulation ilp computer-architecture superscalar branch-prediction rob cpu-architecture instruction-level-parallelism processor-design control-hazards data-hazards out-of-order-execution reorder-buffer register-renaming

Updated Jun 25, 2025
Python

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