The design can split the command into multiple bursts.Only the first burst will be processed, and none of the bursts will cross the 4k boundary. The master_read module support outstanding.There are two versions of slave that support outstanding and not outstanding.Testbench sends the same command to the DMA read/write channel and work on the same area. Some signals are not used,such as CHCHE,LOCK and QOS. The rtl code is written in style of xilinx.
| Name | Description | Default |
|---|---|---|
| AXI_ID_WD | Identification path width in bits. | 2 |
| AXI_DATA_WD | Data path width in bits. | 32 |
| AXI_ADDR_WD | Address path width in bits. | 32 |
| AXI_STRB_WD | Strobe path width in bits. | 4 |
| Name | Direction | Description |
|---|---|---|
| AXI_ACLK | input | All signals and are synchronous to this clock. |
| AXI_ARESETN | input | Resets the internal state of the peripheral. |
| cmd_valid | input | Whether the command is valid |
| cmd_ready | output | Whether the slave is ready |
| cmd_addr | input | The memory address to porcess |
| cmd_id | input | The identification of command |
| cmd_burst | input | Type of burst transter |
| cmd_size | input | The number of bytes transmitted per beat |
| cmd_len | input | The number of bytes to process |
| cmd_abort | output | Signal of error |
