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1. DirectNVM DirectNVM Public archive

   An open-source RTL NVMe controller IP for Xilinx FPGA.

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2. dram_sim_model dram_sim_model Public

   A Xilinx DDR3 simulation model wrapper logic.

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3. LRUCache LRUCache Public

   Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.

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4. SudokuSolver SudokuSolver Public

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5. rtl_template rtl_template Public

   A template folder for Vivado RTL project, including .gitignore.

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6. non-stencil-loop-benchmarks non-stencil-loop-benchmarks Public

   Benchmarks used in our FPGA'19 paper

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