drivers: implement SEC driver #5894

xiaoxuZeng · 2023-03-16T08:10:16Z

Sec is a Security Engine for cipher, digest, HMAC, authenc.

Qm is a queue management device include by Sec.

This PR just implement sec cipher function.

digest, HMAC, authenc. will add on next PR, when we finished development and test.

jenswi-linaro · 2023-03-24T08:08:22Z

What's kunpeng? Are there more kunpengs than HiSilicon kunpengs?

xiaoxuZeng · 2023-03-27T09:11:11Z

What's kunpeng? Are there more kunpengs than HiSilicon kunpengs?

HiSilicon is a vendor, and Kunpeng is a product.
I'll refer to the naming methods of other vendors in the open source community and expect to provide feedback by Wednesday.

Thanks for your review.

jenswi-linaro · 2023-03-27T10:41:41Z

If I've understood it correctly this is all HiSilicon specific. How about putting the files below core/drivers/crypto/hisilicon or core/drivers/crypto/hisi? I'm not sure that further subdirectories are needed.

Public functions and structs prefixed with hisi_. I see that's what you're mostly doing already, but I'd appreciate it if we could be fully consistent.

Public headers (used outside the driver) should preferably go into core/include/drivers/ even if there are examples of public include directories below core/drivers/crypto/. An advantage of keeping public include files below core/include/drivers/ is that it's easier to find things there rather than having to search for .h files all over the place.

Private headers (used inside the driver only) should go into the driver directory and should hopefully not need to be reached outside of that directory.

xiaoxuZeng · 2023-03-28T09:20:40Z

If I've understood it correctly this is all HiSilicon specific. How about putting the files below core/drivers/crypto/hisilicon or core/drivers/crypto/hisi? I'm not sure that further subdirectories are needed.

Public functions and structs prefixed with hisi_. I see that's what you're mostly doing already, but I'd appreciate it if we could be fully consistent.

Public headers (used outside the driver) should preferably go into core/include/drivers/ even if there are examples of public include directories below core/drivers/crypto/. An advantage of keeping public include files below core/include/drivers/ is that it's easier to find things there rather than having to search for .h files all over the place.

Private headers (used inside the driver only) should go into the driver directory and should hopefully not need to be reached outside of that directory.

Thank very much for your patient guidance.

I refer to the Linux community. The directory is hisilicon. Subdirectories are divided by module. Your opinion is absolutely
correct. I plan to use core/drivers/crypto/hisilicon;
The current algorithm file does not use the prefix hisi_. I will change sec_cipher.c to hisi_sec_cipher.c.
The API of SEC is registered into crypto. Currently, the API provided by the QM is invoked only by SEC. Therefore, the two header files are private header files.

Please help me review it at your convenience. Is the above correct?

jenswi-linaro · 2023-03-28T10:49:43Z

I refer to the Linux community. The directory is hisilicon. Subdirectories are divided by module. Your opinion is absolutely
correct. I plan to use core/drivers/crypto/hisilicon;

OK

The current algorithm file does not use the prefix hisi_. I will change sec_cipher.c to hisi_sec_cipher.c.

There's no need to change that since you're using a hisilicon directory. Up to you what you prefer.

The API of SEC is registered into crypto. Currently, the API provided by the QM is invoked only by SEC. Therefore, the two header files are private header files.

All non-static symbols should have a hisi_ prefix, I guess that becomes hisi_sec_ for SEC then. To be sure to avoid conflicts it's good to prefix the private .h files with hisi_ too.

xiaoxuZeng · 2023-04-04T07:24:33Z

If I've understood it correctly this is all HiSilicon specific. How about putting the files below core/drivers/crypto/hisilicon or core/drivers/crypto/hisi? I'm not sure that further subdirectories are needed.

Public functions and structs prefixed with hisi_. I see that's what you're mostly doing already, but I'd appreciate it if we could be fully consistent.

Public headers (used outside the driver) should preferably go into core/include/drivers/ even if there are examples of public include directories below core/drivers/crypto/. An advantage of keeping public include files below core/include/drivers/ is that it's easier to find things there rather than having to search for .h files all over the place.

Private headers (used inside the driver only) should go into the driver directory and should hopefully not need to be reached outside of that directory.

update：
1.Change directory name to hisilicon.
2.All non-static symbols add a hisi_ prefix.

xiaoxuZeng · 2023-04-04T07:26:57Z

The commits with review tag will be rebase into previous commites.

jenswi-linaro · 2023-04-04T14:20:22Z

Please squash in the review commits to make it easier to review the individual commits.

jforissier · 2023-04-06T08:11:55Z

drivers: implement qm driver

drivers: crypto: hisilicon: implement QM driver

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ,

Please define SQ.

and the QM obtains the address of the SQE. The BD information is sent to

Please define SQE and BD.

the accelerator. After the task processing is complete, the accelerator
applies for a write-back address from the QM to write back the SQ.

jforissier · 2023-04-06T08:13:25Z

drivers: implement sec driver

drivers: crypto: hisilicon: implement SEC driver

The Hisilicon SEC(Security Engine) is a hardware security acceleration

Missing space: "SEC (Security Engine)"

module, which is used to enhance the security-related functions of the
processor.

jforissier · 2023-04-06T08:14:19Z

Third commit subject should be "drivers: crypto: hisilicon: implement SEC ciphers".

jforissier · 2023-04-06T08:19:56Z

drivers: implement for kunpeng compile

add compile files for sec qm;

Why not done in the previous commits?

Implement GIC handle for d06;

s/d06/D06/ and should be a separate commit.

Register SEC base address.

I think a better description for what's left would be "d06: crypto: enable SEC acceleration", wouldn't it?

xiaoxuZeng · 2023-04-06T08:22:59Z

drivers: implement for kunpeng compile

add compile files for sec qm;

Why not done in the previous commits?

Implement GIC handle for d06;

s/d06/D06/ and should be a separate commit.

Register SEC base address.

I think a better description for what's left would be "d06: crypto: enable SEC acceleration", wouldn't it?

Good point，I'll deal with it immediately!

jforissier

Comments on "drivers: implement for kunpeng compile".

core/drivers/crypto/sub.mk

core/drivers/crypto/hisilicon/sub.mk

jforissier

Some more comments on "drivers: implement qm driver". Similar comments apply to SEC too.

core/drivers/crypto/hisilicon/qm/hisi_qm.c

etienne-lms · 2023-05-09T07:59:57Z

core/drivers/crypto/hisilicon/hisi_qm.c

@@ -5,6 +5,7 @@
 */
 #include "hisi_qm.h"

+#define CFG_RDY_BIT 0x1


CFG_ prefix is reserved to configuration switches. Use QM_FVT_CFG_RDY_BIT IIUC.

core/drivers/crypto/hisilicon/include/hisi_cipher.h

+	C_MODE_CCM	= 0x5,
+	C_MODE_GCM	= 0x6,
+	C_MODE_XTS	= 0x7,
+	C_MODE_CBC_CS = 0x9,


etienne-lms · 2023-05-09T08:04:45Z

core/drivers/crypto/hisilicon/include/hisi_qm.h

+};
+
+enum hisi_drv_status {
+	DRVCRYPT_NO_ERR = 0,


These are HISI_QM specific error code. Please prefix with HISI_QM_DRVCRYPT_ or like.

etienne-lms · 2023-05-09T08:05:32Z

core/drivers/crypto/hisilicon/include/hisi_qm.h

+	struct hisi_qp *qp_array;
+	struct mutex qp_lock; /* protect the qp instance */
+
+	int32_t (*dev_status_check)(struct hisi_qm *qm);


is expected to return an enum hisi_drv_status, not a raw int32 right?

please fix straight in 1st commit "drivers: crypto: hisilicon: implement QM driver"

etienne-lms · 2023-05-09T08:09:27Z

core/drivers/crypto/hisilicon/include/hisi_qm.h

+ *@param qm: Handle of Queue Management module
+ *@return success: 0，fail: -DRVCRYPT_EBUSY/DRVCRYPT_EINVAL
+ */
+int32_t hisi_qm_init(struct hisi_qm *qm);


Why not returning type enum hisi_drv_status. It would make the implementation better and prevent one messes up between several kinds of return value enums. This comment applies to all hsis_xxx() function returning these error codes.

Note I don't think you need a negative value. Testing a non-zero retrun code would be sufficient to detect an error condition.

core/drivers/crypto/hisilicon/hisi_qm.c

etienne-lms

Main issue to address: many functions are declared to return a TEE_Result value whereas they return an enum hisi_drv_status value.

etienne-lms · 2023-05-22T05:49:04Z

core/arch/arm/include/arm64.h

@@ -288,6 +288,11 @@ static inline __noprof void dsb_ishst(void)
 	asm volatile ("dsb ishst" : : : "memory");
 }

+static inline __noprof void dsb_osh(void)


db_osh() deserves a specific commit.

Great idea, I will handle it as soon as possible.

core/arch/arm/plat-d06/main.c

etienne-lms · 2023-05-22T05:52:03Z

core/drivers/crypto/hisilicon/hisi_qm.c

+{
+	uint32_t val = 0;
+
+	/* return 0 mailbox ready, -ETIMEDOUT hardware timeout */


this function is expected to return a TEE_result compliant value.

Did I misunderstand your meaning?

static TEE_Result qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr, uint16_t qn, uint8_t op)

to

static enum hisi_drv_status qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr, uint16_t qn, uint8_t op)

Is this what you meant? @etienne-lms

Sorry if I was not very clear. I'll try to make it short
The many functions that return a value like HISI_QM_DRVCRYPT_xxx should be declared as:
enum hisi_drv_status <function_label>(...).
All functions that return a value like TEE_SUCCESS or TEE_ERROR_xxxshould be declared as:TEE_Result <function_label>(...)`
Make sure not to mix both unless what return values are not reliable.

I think I understand now. Thank you for your patient explanation. I will handle it as soon as possible!

core/drivers/crypto/hisilicon/hisi_qm.c

+
+	if (qm_wait_mb_ready(qm)) {
+		EMSG("QM mailbox is busy");
+		return HISI_QM_DRVCRYPT_EBUSY;


etienne-lms · 2023-05-22T05:54:55Z

core/drivers/crypto/hisilicon/hisi_qm.c

+	case QM_SQC_VFT:
+		data = (SHIFT_U64(base, QM_SQC_VFT_START_SQN_SHIFT) |
+			QM_SQC_VFT_VALID |
+			SHIFT_U64((number - 1), QM_SQC_VFT_SQ_NUM_SHIFT));


can remove outer parentheses

core/drivers/crypto/hisilicon/sec/sec_cipher.c

etienne-lms · 2023-05-22T07:07:58Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+{
+	struct sec_cipher_ctx *c_ctx = NULL;
+	size_t padding_size = 0;
+	TEE_Result ret = 0;


prefer use a TEE_Result defined value rather than 0. E.g. TEE_SUCCESS, or TEE_ERROR_GENERIC, or ...

etienne-lms · 2023-05-22T07:10:34Z

core/drivers/crypto/hisilicon/sec/hisi_sec.c

+	struct acc_device *sec_dev = NULL, *cur_dev = NULL;
+	uint32_t max_qp_num = 0;
+	uint32_t free_qp_num;
+	struct hisi_qm *qm;


init values

etienne-lms · 2023-05-22T07:11:06Z

core/drivers/crypto/hisilicon/sec/hisi_sec.c

+{
+	struct hisi_qm *qm = &sec_dev->qm;
+	uint32_t val = 0;
+	uint32_t ret = 0;


Recommendation: enum hisi_drv_status ret = HISI_QM_DRVCRYPT_NO_ERRere and at many other places.

etienne-lms · 2023-05-22T07:12:58Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+	uint8_t t = 0;
+	int i = 0;
+
+	for (i = 0, t = 0; i < AES_SM4_IV_SIZE; i++) {


can remove t = 0, it is already inittialilzed to 0.

etienne-lms · 2023-05-30T08:12:39Z

core/arch/arm/plat-d06/main.c


 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, LPC_BASE, LPC_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, SEC_BASE, SEC_SIZE);
+
+void itr_core_handler(void)


please rebase in master tip. Platforms no more need to implement itr_core_handler() since #6030 has been merged.

I'll do it as soon as possible.

etienne-lms · 2023-05-30T08:13:06Z

core/drivers/crypto/hisilicon/crypto.mk

+
+$(call force,CFG_CRYPTO_DRIVER,y)
+CFG_CRYPTO_DRIVER_DEBUG ?= 0
+


nitpicking: i suggestion to remove the empty lines above and below.

No, is a kind suggestion, thx

etienne-lms · 2023-05-30T08:15:26Z

core/drivers/crypto/hisilicon/hisi_qm.c

+ */
+#include "hisi_qm.h"
+
+#define QM_FVT_CFG_RDY_BIT 0x1


nitpicking: using a tabulation bewteen macro name and assigned value make the file easier to read:

#define QM_FVT_CFG_RDY_BIT 0x1 /* Doorbell */ #define QM_DOORBELL_SQ_CQ_BASE 0x1000 #define QM_DB_CMD_SHIFT 12 #define QM_DB_RAND_DATA_SHIFT 16 #define QM_DB_INDEX_SHIFT 32 #define QM_DB_PRIORITY_SHIFT 48 #define QM_DB_RAND_DATA 0x5a #define QM_DOORBELL_CMD_SQ 0 #define QM_DOORBELL_CMD_CQ 1 (...)

etienne-lms · 2023-05-30T08:16:42Z

core/drivers/crypto/hisilicon/hisi_qm.c

+	{.reg_name = "QM_DFX_WB_SQE_FROM_ACC_CNT",  .reg_offset = 0x104058},
+	{.reg_name = "QM_DFX_ACC_FINISH_CNT     ",  .reg_offset = 0x104060},
+	{.reg_name = "QM_DFX_CQE_ERR_CNT        ",  .reg_offset = 0x1040b4},
+	{.reg_name =  NULL, 0}


could replace all 2 space chars with a signle one (applies from line 109 to line 119).

sorry, on coding style, add a space char after an opening brace { and another space char before the closing brace }.

{ .reg_name = "QM_DFX_ACC_FINISH_CNT ", .reg_offset = 0x104060 }, { .reg_name = "QM_DFX_CQE_ERR_CNT ", .reg_offset = 0x1040b4 }, { .reg_name = NULL, 0 }

core/drivers/crypto/hisilicon/hisi_qm.c

+{
+	uint32_t val = 0;
+
+	/* return 0 mailbox ready, HISI_QM_DRVCRYPT_ETMOUT hardware timeout */


etienne-lms · 2023-05-30T09:11:28Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+	}
+
+	ret = cipher_algo_check(algo);
+	if (ret != 0)


s/ret != 0/ret/

etienne-lms · 2023-05-30T09:12:01Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+	}
+
+	c_ctx->offs = 0;
+	(*ctx) = c_ctx;


parentheses not needed

etienne-lms · 2023-05-30T09:13:04Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+		return;
+
+	hisi_qm_release_qp(c_ctx->qp);
+	memset(c_ctx->key, 0, c_ctx->key_len);


should use memzero_explicit() instead of memset().

etienne-lms · 2023-05-30T09:13:25Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+static TEE_Result sec_cipher_init(struct drvcrypt_cipher_init *dinit)
+{
+	struct sec_cipher_ctx *c_ctx = NULL;
+	TEE_Result ret = 0;


= TEE_SUCCESS

etienne-lms · 2023-05-30T09:14:53Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c

+	       dupdate->src.data, dupdate->src.length);
+
+	ret = sec_do_cipher_task(c_ctx->qp, c_ctx);
+	if (ret != 0)


s/ret != 0/ret/ here and at all other places where applicable.

etienne-lms · 2023-06-07T06:57:56Z

@xiaoxuZeng, please don't use commit merge in your patch series. You need to rebase your series on top of master branch tip instead.

etienne-lms

I found some issues. Please rebase your changes, i'll review them afterward.

etienne-lms · 2023-06-06T12:07:22Z

core/drivers/crypto/hisilicon/sec/sec_cipher.c


-	if (!iv && iv_len != 0) {
-		EMSG("Iv is NULL");
+	if (!iv && iv_len != TEE_SUCCESS) {


typo: iv_len is not a TEE_Resuslt value.
Replace with if (!iv && iv_len)

etienne-lms · 2023-06-06T12:09:31Z

core/drivers/crypto/hisilicon/include/hisi_qm.h

+	paddr_t sqe_dma;
+	paddr_t cqe_dma;
+
+	enum TEE_Result (*fill_sqe)(void *sqe, void *msg);


s/TEE_Result/enum hisi_drv_status/

Ditto at line below.

etienne-lms · 2023-06-06T12:12:36Z

core/drivers/crypto/hisilicon/include/hisi_sec.h

+#define __HISI_SEC_H__
+
+#include "hisi_qm.h"
+#include <initcall.h>


swap the 2 lines.
include <> first, then include "".

xiaoxuZeng · 2023-06-19T09:30:08Z

@xiaoxuZeng, please don't use commit merge in your patch series. You need to rebase your series on top of master branch tip instead.

I will handle it as soon as possible. Thank you!

etienne-lms · 2023-07-05T11:59:44Z

@xiaoxuZeng, please don't use commit merges in your patch series. You need to rebase your series on top of master branch tip instead.

jenswi-linaro · 2023-07-13T09:07:42Z

For commit "core: arm64: add dsb_osh", in the description I think it should say "osh data barrier" instead of "ishst memory barrier". Feel free to create a new pull request with this commit only. That would allow getting that commit merged before the rest of this PR and help the reviewing a little bit.

xiaoxuZeng · 2023-07-14T09:46:26Z

For commit "core: arm64: add dsb_osh", in the description I think it should say "osh data barrier" instead of "ishst memory barrier". Feel free to create a new pull request with this commit only. That would allow getting that commit merged before the rest of this PR and help the reviewing a little bit.

yeh, I have created a new PR, Thanks.
#6176

The Hisilicon QM is a Queue Management module. In order to unify the interface between accelerator and software, a unified queue management module QM is used to interact with software. Each accelerator module integrates a QM. Software issues tasks to the SQ (Submmision Queue),and the QM obtains the address of the SQE (Submmision Queue Element). The BD (Buffer Description, same as SQE) information is sent to the accelerator. After the task processing is complete, the accelerator applies for a write-back address from the QM to write back the SQ. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>

The Hisilicon SEC (Security Engine) is a hardware security acceleration module, which is used to enhance the security-related functions of the processor. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>

Add the Hisilicon SEC as a drvcrypt cipher provider. Supported for DES-ECB/CBC 3DES-ECB/CBC AES-ECB/CBC/CTR SM4-ECB/CBC/CTR. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>

github-actions · 2023-08-31T01:20:26Z

This pull request has been marked as a stale pull request because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this pull request will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time.

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xiaoxuZeng added 3 commits July 18, 2023 10:33

drivers: crypto: hisilicon: implement SEC driver

f8a7eef

The Hisilicon SEC (Security Engine) is a hardware security acceleration module, which is used to enhance the security-related functions of the processor. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>

drivers: crypto: hisilicon: implement SEC ciphers

999da9d

Add the Hisilicon SEC as a drvcrypt cipher provider. Supported for DES-ECB/CBC 3DES-ECB/CBC AES-ECB/CBC/CTR SM4-ECB/CBC/CTR. Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>

xiaoxuZeng reopened this Jul 18, 2023

xiaoxuZeng requested review from jenswi-linaro, etienne-lms and jforissier July 27, 2023 06:55

xiaoxuZeng mentioned this pull request Aug 2, 2023

drivers: crypto: hisilicon: implement QM driver #6212

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github-actions bot added the Stale label Aug 31, 2023

github-actions bot closed this Sep 6, 2023


		$(call force,CFG_CRYPTO_DRIVER,y)
		CFG_CRYPTO_DRIVER_DEBUG ?= 0

drivers: implement SEC driver #5894

drivers: implement SEC driver #5894

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