Fix test

Xilinx · Oct 30, 2024 · 21064be · 21064be
1 parent de08230
commit 21064be
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/test/objectFifo-stateful-transform/init_values_test.mlir b/test/objectFifo-stateful-transform/init_values_test.mlir
@@ -21,9 +21,9 @@
 // CHECK:     %of0_cons_buff_2 = aie.buffer(%tile_2_3) {sym_name = "of0_cons_buff_2"} : memref<2x2xi32> 
 // CHECK:     %of0_cons_prod_lock = aie.lock(%tile_2_3, 0) {init = 3 : i32, sym_name = "of0_cons_prod_lock"}
 // CHECK:     %of0_cons_cons_lock = aie.lock(%tile_2_3, 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"}
-// CHECK:     %of0_buff_0 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_0"} : memref<2x2xi32> = dense<[[0, 1], [2, 3]]>
-// CHECK:     %of0_buff_1 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_1"} : memref<2x2xi32> = dense<[[4, 5], [6, 7]]>
-// CHECK:     %of0_buff_2 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_2"} : memref<2x2xi32> = dense<[[8, 9], [10, 11]]>
+// CHECK:     %of0_buff_0 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_0"} : memref<2x2xi32> = dense<{{\[}}[0, 1], [2, 3]]>
+// CHECK:     %of0_buff_1 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_1"} : memref<2x2xi32> = dense<{{\[}}[4, 5], [6, 7]]>
+// CHECK:     %of0_buff_2 = aie.buffer(%tile_1_2) {sym_name = "of0_buff_2"} : memref<2x2xi32> = dense<{{\[}}[8, 9], [10, 11]]>
 // CHECK:     %of0_prod_lock = aie.lock(%tile_1_2, 0) {init = 0 : i32, sym_name = "of0_prod_lock"}
 // CHECK:     %of0_cons_lock = aie.lock(%tile_1_2, 1) {init = 3 : i32, sym_name = "of0_cons_lock"}
 // CHECK:     aie.flow(%tile_1_2, DMA : 0, %tile_2_3, DMA : 0)