Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[ROCm] Add pieces from the CUDA codgen lowering path #14769

Merged
merged 2 commits into from
Sep 8, 2023
Merged

[ROCm] Add pieces from the CUDA codgen lowering path #14769

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
f739810
[ROCm] Add pieces from the CUDA codgen lowering path
sogartar Aug 21, 2023
63fce95
Move DropSharedMemoryDeallocOp out of header (to squash)
sogartar Aug 22, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 0 additions & 16 deletions compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToNVVM.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,22 +38,6 @@ namespace iree_compiler {

namespace {

// A `dealloc` is converted into a call to `free` on the underlying data buffer.
// The memref descriptor being an SSA value, there is no need to clean it up
// in any way.
struct DropSharedMemoryDeallocOp : public OpRewritePattern<memref::DeallocOp> {
using OpRewritePattern::OpRewritePattern;

LogicalResult matchAndRewrite(memref::DeallocOp op,
PatternRewriter &rewriter) const override {
if (!hasSharedMemoryAddressSpace(
llvm::cast<MemRefType>(op.getMemref().getType())))
return failure();
rewriter.eraseOp(op);
return success();
}
};

/// A pass that replaces all occurrences of GPU device operations with their
/// corresponding NVVM equivalent.
///
Expand Down
8 changes: 3 additions & 5 deletions compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
#include "iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.h"
#include "iree/compiler/Codegen/LLVMGPU/PassDetail.h"
#include "iree/compiler/Codegen/LLVMGPU/Passes.h"
#include "iree/compiler/Codegen/Utils/GPUUtils.h"
#include "iree/compiler/Codegen/Utils/Utils.h"
#include "iree/compiler/Dialect/Util/IR/UtilOps.h"
#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h"
Expand Down Expand Up @@ -69,6 +70,7 @@ struct ConvertToROCDLPass : public ConvertToROCDLBase<ConvertToROCDLPass> {
// Run Vector -> Vector transformations ahead of conversion to LLVM.
{
RewritePatternSet patterns(&getContext());
patterns.insert<DropSharedMemoryDeallocOp>(&getContext());
populateScalarizeMathOps(patterns);
populateConvertSharedMemoryAllocOps(patterns);
vector::populateVectorToVectorCanonicalizationPatterns(patterns);
Expand Down Expand Up @@ -112,14 +114,10 @@ struct ConvertToROCDLPass : public ConvertToROCDLBase<ConvertToROCDLPass> {
LLVMConversionTarget target(getContext());
populateFuncToLLVMFuncOpConversionPattern(converter, llvmPatterns);
configureGpuToROCDLConversionLegality(target);
target.addDynamicallyLegalOp<func::FuncOp>([&](func::FuncOp funcOp) {
if (isEntryPoint(funcOp))
return false;
return true;
});
if (failed(applyPartialConversion(m, target, std::move(llvmPatterns))))
signalPassFailure();
}
ConvertToDynamicSharedMemory(m);
}
};

Expand Down
3 changes: 1 addition & 2 deletions compiler/src/iree/compiler/Codegen/LLVMGPU/Passes.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -552,8 +552,7 @@ static void addLowerToLLVMGPUPasses(OpPassManager &pm, bool useROCM) {
// debug info well.
pm.addPass(createStripDebugInfoPass());
// Cast address spaces of all function arguments to generic
if (!useROCM)
pm.addPass(createLLVMGPUCastAddressSpaceFunction());
pm.addPass(createLLVMGPUCastAddressSpaceFunction());
if (useROCM) {
// convert to ROCDL.
pm.addPass(createConvertToROCDLPass());
Expand Down
10 changes: 10 additions & 0 deletions compiler/src/iree/compiler/Codegen/Utils/GPUUtils.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -359,6 +359,16 @@ Value unpackToVector(Location loc, OpBuilder &builder, Value packedInput,
return unpackedVector;
}

LogicalResult
DropSharedMemoryDeallocOp::matchAndRewrite(memref::DeallocOp op,
PatternRewriter &rewriter) const {
if (!hasSharedMemoryAddressSpace(
llvm::cast<MemRefType>(op.getMemref().getType())))
return failure();
rewriter.eraseOp(op);
return success();
}

/// Emit warp reduction code sequence for a given input.
static Value warpReduction(Location loc, OpBuilder &builder, Value input,
vector::CombiningKind kind, uint32_t warpSize,
Expand Down
11 changes: 11 additions & 0 deletions compiler/src/iree/compiler/Codegen/Utils/GPUUtils.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#include "iree/compiler/Codegen/Utils/Utils.h"
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/Dialect/Vector/IR/VectorOps.h"
#include "mlir/IR/PatternMatch.h"
namespace mlir {
namespace iree_compiler {

Expand Down Expand Up @@ -101,6 +102,16 @@ Value packVectorToSupportedWidth(Location loc, OpBuilder &builder, Value input);
Value unpackToVector(Location loc, OpBuilder &builder, Value packedInput,
VectorType targetVecType);

// A `dealloc` is converted into a call to `free` on the underlying data buffer.
// The memref descriptor being an SSA value, there is no need to clean it up
// in any way.
struct DropSharedMemoryDeallocOp : public OpRewritePattern<memref::DeallocOp> {
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

THe norm is to not have the pattern exposed directly this way. Could you move these patterns to Common/GPU and use a populateDropSharedMemoryDeallocPatterns method to add these patterns to both paths?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I moved it.

using OpRewritePattern::OpRewritePattern;

LogicalResult matchAndRewrite(memref::DeallocOp op,
PatternRewriter &rewriter) const override;
};

//===----------------------------------------------------------------------===//
// GPU CodeGen op filter
//===----------------------------------------------------------------------===//
Expand Down