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Add Zfhmin support
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@jordancarlin
jordancarlin committed Oct 20, 2024
1 parent 2a2a950 commit 247339f
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Showing 2 changed files with 20 additions and 16 deletions.
12 changes: 8 additions & 4 deletions model/riscv_insts_fext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,10 @@
enum clause extension = Ext_Zfh
function clause extensionEnabled(Ext_Zfh) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)

enum clause extension = Ext_Zfhmin
// Zfhmin is a subset of Zfh. This can be changed to extensionEnabled(Ext_Zfh) | sys_enable_zfhmin() when more configuration is implemented.
function clause extensionEnabled(Ext_Zfhmin) = extensionEnabled(Ext_Zfh)

mapping encdec_rounding_mode : rounding_mode <-> bits(3) = {
RM_RNE <-> 0b000,
RM_RTZ <-> 0b001,
Expand Down Expand Up @@ -274,8 +278,8 @@ union clause ast = LOAD_FP : (bits(12), regidx, regidx, word_width)

/* AST <-> Binary encoding ================================ */

mapping clause encdec = LOAD_FP(imm, rs1, rd, HALF) if extensionEnabled(Ext_Zfh)
<-> imm @ rs1 @ 0b001 @ rd @ 0b000_0111 if extensionEnabled(Ext_Zfh)
mapping clause encdec = LOAD_FP(imm, rs1, rd, HALF) if extensionEnabled(Ext_Zfhmin)
<-> imm @ rs1 @ 0b001 @ rd @ 0b000_0111 if extensionEnabled(Ext_Zfhmin)

mapping clause encdec = LOAD_FP(imm, rs1, rd, WORD) if extensionEnabled(Ext_F)
<-> imm @ rs1 @ 0b010 @ rd @ 0b000_0111 if extensionEnabled(Ext_F)
Expand Down Expand Up @@ -360,8 +364,8 @@ union clause ast = STORE_FP : (bits(12), regidx, regidx, word_width)

/* AST <-> Binary encoding ================================ */

mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, HALF) if extensionEnabled(Ext_Zfh)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b001 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_Zfh)
mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, HALF) if extensionEnabled(Ext_Zfhmin)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b001 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_Zfhmin)

mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, WORD) if extensionEnabled(Ext_F)
<-> imm7 : bits(7) @ rs2 @ rs1 @ 0b010 @ imm5 : bits(5) @ 0b010_0111 if extensionEnabled(Ext_F)
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24 changes: 12 additions & 12 deletions model/riscv_insts_zfh.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -538,20 +538,20 @@ mapping clause encdec =
<-> 0b110_1010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()

mapping clause encdec =
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_S) if haveHalfFPU()
<-> 0b010_0010 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_S) if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)
<-> 0b010_0010 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)

mapping clause encdec =
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_D) if haveHalfFPU()
<-> 0b010_0010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_D) if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)
<-> 0b010_0010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)

mapping clause encdec =
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_S_H) if haveHalfFPU()
<-> 0b010_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_S_H) if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)
<-> 0b010_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)

mapping clause encdec =
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_D_H) if haveHalfFPU()
<-> 0b010_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()
F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_D_H) if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)
<-> 0b010_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() | extensionEnabled(Ext_Zfhmin)

// TODO:
/* FCVT_H_Q, FCVT_Q_H : Will be added with Q Extension */
Expand Down Expand Up @@ -884,11 +884,11 @@ union clause ast = F_UN_TYPE_H : (regidx, regidx, f_un_op_H)
mapping clause encdec = F_UN_TYPE_H(rs1, rd, FCLASS_H) if haveHalfFPU()
<-> 0b111_0010 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveHalfFPU()

mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_X_H) if extensionEnabled(Ext_Zfh)
<-> 0b111_0010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_Zfh)
mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_X_H) if extensionEnabled(Ext_Zfhmin)
<-> 0b111_0010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_Zfhmin)

mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_H_X) if extensionEnabled(Ext_Zfh)
<-> 0b111_1010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_Zfh)
mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_H_X) if extensionEnabled(Ext_Zfhmin)
<-> 0b111_1010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_Zfhmin)

/* Execution semantics ================================ */

Expand Down

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