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    • RISC-V Opcodes
      Python
      BSD 3-Clause "New" or "Revised" License
      3006912424Updated Oct 31, 2024Oct 31, 2024
    • The ISA specification for the Zalasr extension.
      Makefile
      Creative Commons Attribution 4.0 International
      1130Updated Oct 31, 2024Oct 31, 2024
    • learn

      Public
      Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
      6353701Updated Oct 31, 2024Oct 31, 2024
    • Sail RISC-V model
      Coq
      Other
      1644549061Updated Oct 31, 2024Oct 31, 2024
    • This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      Makefile
      Creative Commons Attribution 4.0 International
      153801Updated Oct 31, 2024Oct 31, 2024
    • This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      Python
      Creative Commons Attribution 4.0 International
      2950357Updated Oct 30, 2024Oct 30, 2024
    • RISC-V Self-hosted Trace Development Repositoty
      TeX
      Creative Commons Attribution 4.0 International
      639000Updated Oct 30, 2024Oct 30, 2024
    • RISC-V Configuration Structure
      Python
      Creative Commons Attribution 4.0 International
      1736141Updated Oct 30, 2024Oct 30, 2024
    • RISC-V Instruction Set Manual
      TeX
      Creative Commons Attribution 4.0 International
      6393.7k19215Updated Oct 28, 2024Oct 28, 2024
    • RISC-V Architecture Profiles
      Makefile
      Creative Commons Attribution 4.0 International
      33116101Updated Oct 28, 2024Oct 28, 2024
    • A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      7903Updated Oct 28, 2024Oct 28, 2024
    • OpenEmbedded/Yocto layer for RISC-V Architecture
      BitBake
      Other
      140364174Updated Oct 25, 2024Oct 25, 2024
    • RISC-V Performance Events Specification
      Python
      Creative Commons Attribution 4.0 International
      2450Updated Oct 25, 2024Oct 25, 2024
    • This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      Creative Commons Attribution 4.0 International
      41700Updated Oct 24, 2024Oct 24, 2024
    • Working Draft of the RISC-V J Extension Specification
      Makefile
      Creative Commons Attribution 4.0 International
      1716753Updated Oct 16, 2024Oct 16, 2024
    • Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      Creative Commons Attribution 4.0 International
      1611Updated Oct 11, 2024Oct 11, 2024
    • Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      Creative Commons Attribution 4.0 International
      49245362Updated Oct 3, 2024Oct 3, 2024
    • Creative Commons Attribution 4.0 International
      142431Updated Oct 1, 2024Oct 1, 2024
    • RISC-V Integrated Matrix Development Repository
      TeX
      Creative Commons Attribution 4.0 International
      639200Updated Sep 30, 2024Sep 30, 2024
    • Documentation developer guide
      TeX
      Creative Commons Attribution 4.0 International
      308620Updated Sep 30, 2024Sep 30, 2024
    • Trigger Delegation Fast-Track Specification
      TeX
      Creative Commons Attribution 4.0 International
      639001Updated Sep 26, 2024Sep 26, 2024
    • Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      2750Updated Sep 18, 2024Sep 18, 2024
    • Working Draft of the RISC-V Debug Specification Standard
      Python
      Other
      92456535Updated Sep 12, 2024Sep 12, 2024
    • The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      Creative Commons Attribution 4.0 International
      71121Updated Sep 10, 2024Sep 10, 2024
    • Makefile
      55101Updated Sep 5, 2024Sep 5, 2024
    • riscv-aia

      Public
      Creative Commons Attribution 4.0 International
      1979274Updated Aug 29, 2024Aug 29, 2024
    • RISC-V Double Trap Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      31200Updated Aug 23, 2024Aug 23, 2024
    • docs-spec-template

      Public template
      Makefile
      Creative Commons Attribution 4.0 International
      191811Updated Aug 15, 2024Aug 15, 2024
    • This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      Creative Commons Attribution 4.0 International
      0110Updated Jul 19, 2024Jul 19, 2024
    • Dot-Product Extension
      Makefile
      Creative Commons Attribution 4.0 International
      2211Updated Jul 16, 2024Jul 16, 2024