cetrig should be WARL

riscv · Jul 10, 2024 · a5c8c29 · a5c8c29
1 parent b7df096
commit a5c8c29
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/xml/core_registers.xml b/xml/core_registers.xml
@@ -84,7 +84,7 @@ same project unless stated otherwise.
             for use by other RISC-V extensions.
         </field>
         <field name="0" bits="23:20" access="R" reset="0" />
-        <field name="cetrig" bits="19" access="R/W" reset="0">
+        <field name="cetrig" bits="19" access="WARL" reset="0">
             This bit is part of ((Smdbltrp)) and only exists when that extension
             is implemented.