Move extcause, and don't reserve any values.

Based on feedback from Ved.

xml/core_registers.xml

@@ -70,19 +70,15 @@ same project unless stated otherwise.
             available version of this spec.
             </value>
         </field>
-        <field name="0" bits="27:21" access="R" reset="0" />
-        <field name="extcause" bits="20:18" access="R" reset="0">
+        <field name="0" bits="27" access="R" reset="0" />
+        <field name="extcause" bits="26:24" access="R" reset="0">
             When {dcsr-cause} is 7, this optional field contains the value of a
             more specific halt reason than "other." Otherwise it contains 0.
 
-            <value v="0" name="none">
-            There is no more specific halt reason, probably because the hardware
-            does not implement this field.
-            </value>
-
-            Other values are reserved for future versions of this spec, or for
-            use by other RISC-V extensions.
+            All values are reserved for future versions of this spec, or for use
+            by other RISC-V extensions.
         </field>
+        <field name="0" bits="23:18" access="R" reset="0" />
         <field name="ebreakvs" bits="17" access="WARL" reset="0">
             <value v="0" name="exception">
             `ebreak` instructions in VS-mode behave as described in the