Add support for upcoming cocotb 2.0

cocotb_test/compat.py

@@ -0,0 +1,11 @@
+
+from packaging.version import parse as parse_version
+import cocotb
+
+# Use 1.999.0 in comparison to match pre-release versions of cocotb too
+cocotb_2x_or_newer = parse_version(cocotb.__version__) > parse_version("1.999.0")
+
+if cocotb_2x_or_newer:
+    import cocotb_tools.config as cocotb_config
+else:
+    import cocotb.config as cocotb_config

cocotb_test/simulator.py

@@ -10,9 +10,9 @@
 import signal
 import warnings
 import find_libpython
-import cocotb.config
 import asyncio
 import sysconfig
+from cocotb_test.compat import cocotb_2x_or_newer, cocotb_config
 
 _magic_re = re.compile(r"([\\{}])")
 _space_re = re.compile(r"([\s])", re.ASCII)
@@ -174,8 +174,8 @@ def set_env(self):
 
         self.env["PYTHONHOME"] = sysconfig.get_config_var("prefix")
 
-        self.env["TOPLEVEL"] = self.toplevel_module
-        self.env["MODULE"] = self.module
+        self.env["COCOTB_TOPLEVEL" if cocotb_2x_or_newer else "TOPLEVEL"] = self.toplevel_module
+        self.env["COCOTB_TEST_MODULES" if cocotb_2x_or_newer else "MODULE"] = self.module
 
         if not os.path.exists(self.sim_dir):
             os.makedirs(self.sim_dir)
@@ -443,7 +443,7 @@ def compile_command(self):
 
     def run_command(self):
         return (
-            ["vvp", "-M", self.lib_dir, "-m", cocotb.config.lib_name("vpi", "icarus")]
+            ["vvp", "-M", self.lib_dir, "-m", cocotb_config.lib_name("vpi", "icarus")]
             + self.simulation_args
             + [self.sim_file]
             + self.plus_args
@@ -553,23 +553,23 @@ def build_command(self):
                     + ["-onfinish", "stop" if self.gui else "exit"]
                     + [
                         "-foreign",
-                        "cocotb_init " + as_tcl_value(cocotb.config.lib_name_path("fli", "questa")),
+                        "cocotb_init " + as_tcl_value(cocotb_config.lib_name_path("fli", "questa")),
                     ]
                     + self.simulation_args
                     + [as_tcl_value(v) for v in self.get_parameter_commands(self.parameters)]
                     + self.toplevel
                     + ["-do", do_script]
                 )
                 if self.verilog_sources:
-                    self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vpi", "questa") + ":cocotbvpi_entry_point"
+                    self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vpi", "questa") + ":cocotbvpi_entry_point"
             else:
                 cmd.append(
                     ["vsim"]
                     + ["-gui" if self.gui else "-c"]
                     + ["-onfinish", "stop" if self.gui else "exit"]
                     + [
                         "-pli",
-                        as_tcl_value(cocotb.config.lib_name_path("vpi", "questa")),
+                        as_tcl_value(cocotb_config.lib_name_path("vpi", "questa")),
                     ]
                     + self.simulation_args
                     + [as_tcl_value(v) for v in self.get_parameter_commands(self.parameters)]
@@ -578,7 +578,7 @@ def build_command(self):
                     + ["-do", do_script]
                 )
                 if self.vhdl_sources:
-                    self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("fli", "questa") + ":cocotbfli_entry_point"
+                    self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("fli", "questa") + ":cocotbfli_entry_point"
 
         return cmd
 
@@ -592,7 +592,7 @@ class Ius(Simulator):
     def __init__(self, *argv, **kwargs):
         super().__init__(*argv, **kwargs)
 
-        self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vhpi", "ius") + ":cocotbvhpi_entry_point"
+        self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vhpi", "ius") + ":cocotbvhpi_entry_point"
 
     def get_include_commands(self, includes):
         include_cmd = []
@@ -639,7 +639,7 @@ def build_command(self):
                     "-define",
                     "COCOTB_SIM=1",
                     "-loadvpi",
-                    cocotb.config.lib_name_path("vpi", "ius") + ":vlog_startup_routines_bootstrap",
+                    cocotb_config.lib_name_path("vpi", "ius") + ":vlog_startup_routines_bootstrap",
                     "-plinowarn",
                     "-access",
                     "+rwc",
@@ -674,7 +674,7 @@ class Xcelium(Simulator):
     def __init__(self, *argv, **kwargs):
         super().__init__(*argv, **kwargs)
 
-        self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vhpi", "xcelium") + ":cocotbvhpi_entry_point"
+        self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vhpi", "xcelium") + ":cocotbvhpi_entry_point"
 
     def get_include_commands(self, includes):
         include_cmd = []
@@ -721,7 +721,7 @@ def build_command(self):
                     "-define",
                     "COCOTB_SIM=1",
                     "-loadvpi",
-                    cocotb.config.lib_name_path("vpi", "xcelium") + ":vlog_startup_routines_bootstrap",
+                    cocotb_config.lib_name_path("vpi", "xcelium") + ":vlog_startup_routines_bootstrap",
                     "-plinowarn",
                     "-access",
                     "+rwc",
@@ -792,7 +792,7 @@ def build_command(self):
                 "pli.tab",
                 "+define+COCOTB_SIM=1",
                 "-load",
-                cocotb.config.lib_name_path("vpi", "vcs"),
+                cocotb_config.lib_name_path("vpi", "vcs"),
                 "-top",
                 self.toplevel_module,
             ]
@@ -857,7 +857,7 @@ def build_command(self):
             ["ghdl", "-r", f"--work={self.toplevel_library}"]
             + compile_args
             + [self.toplevel_module]
-            + ["--vpi=" + cocotb.config.lib_name_path("vpi", "ghdl")]
+            + ["--vpi=" + str(cocotb_config.lib_name_path("vpi", "ghdl"))]
             + self.simulation_args
             + self.get_parameter_commands(self.parameters)
         )
@@ -903,7 +903,7 @@ def build_command(self):
             + ["-L", self.sim_dir, "--stderr=error"]
             + ["-r"]
             + [self.toplevel_module]
-            + ["--load", cocotb.config.lib_name_path("vhpi", "nvc")]
+            + ["--load", cocotb_config.lib_name_path("vhpi", "nvc")]
             + self.simulation_args
         )
 
@@ -960,25 +960,25 @@ def build_command(self):
                 do_script += "asim +access +w -interceptcoutput -O2 -loadvhpi {EXT_NAME} {EXTRA_ARGS} {RTL_LIBRARY}.{TOPLEVEL} \n".format(
                     RTL_LIBRARY=as_tcl_value(self.rtl_library),
                     TOPLEVEL=as_tcl_value(self.toplevel_module),
-                    EXT_NAME=as_tcl_value(cocotb.config.lib_name_path("vhpi", "riviera") + ":vhpi_startup_routines_bootstrap"),
+                    EXT_NAME=as_tcl_value(cocotb_config.lib_name_path("vhpi", "riviera") + ":vhpi_startup_routines_bootstrap"),
                     EXTRA_ARGS=" ".join(
                         as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))
                     ),
                 )
                 if self.verilog_sources:
-                    self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vpi", "riviera") + "cocotbvpi_entry_point"
+                    self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vpi", "riviera") + "cocotbvpi_entry_point"
             else:
                 do_script += "asim +access +w -interceptcoutput -O2 -pli {EXT_NAME} {EXTRA_ARGS} {RTL_LIBRARY}.{TOPLEVEL} {PLUS_ARGS} \n".format(
                     RTL_LIBRARY=as_tcl_value(self.rtl_library),
                     TOPLEVEL=as_tcl_value(self.toplevel_module),
-                    EXT_NAME=as_tcl_value(cocotb.config.lib_name_path("vpi", "riviera")),
+                    EXT_NAME=as_tcl_value(cocotb_config.lib_name_path("vpi", "riviera")),
                     EXTRA_ARGS=" ".join(
                         as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))
                     ),
                     PLUS_ARGS=" ".join(as_tcl_value(v) for v in self.plus_args),
                 )
                 if self.vhdl_sources:
-                    self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vhpi", "riviera") + ":cocotbvhpi_entry_point"
+                    self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vhpi", "riviera") + ":cocotbvhpi_entry_point"
 
             if self.waves:
                 do_script += "trace -recursive /*;"
@@ -1046,25 +1046,25 @@ def build_script_sim(self):
                     RTL_LIBRARY=as_tcl_value(self.rtl_library),
                     TOPLEVEL=as_tcl_value(self.toplevel_module),
                     EXT_NAME=as_tcl_value(
-                        cocotb.config.lib_name_path("vhpi", "activehdl") + ":vhpi_startup_routines_bootstrap"
+                        cocotb_config.lib_name_path("vhpi", "activehdl") + ":vhpi_startup_routines_bootstrap"
                     ),
                     EXTRA_ARGS=" ".join(self.simulation_args + self.get_parameter_commands(self.parameters)),
                 )
             )
             if self.verilog_sources:
-                self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vpi", "activehdl") + "cocotbvpi_entry_point"
+                self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vpi", "activehdl") + "cocotbvpi_entry_point"
         else:
             do_script += 'asim +access +w -interceptcoutput -O2 -pli "{EXT_NAME}" {EXTRA_ARGS} {RTL_LIBRARY}.{TOPLEVEL} {PLUS_ARGS} \n'.format(
                 RTL_LIBRARY=as_tcl_value(self.rtl_library),
                 TOPLEVEL=as_tcl_value(self.toplevel_module),
-                EXT_NAME=as_tcl_value(cocotb.config.lib_name_path("vpi", "activehdl")),
+                EXT_NAME=as_tcl_value(cocotb_config.lib_name_path("vpi", "activehdl")),
                 EXTRA_ARGS=" ".join(
                     as_tcl_value(v) for v in (self.simulation_args + self.get_parameter_commands(self.parameters))
                 ),
                 PLUS_ARGS=" ".join(as_tcl_value(v) for v in self.plus_args),
             )
             if self.vhdl_sources:
-                self.env["GPI_EXTRA"] = cocotb.config.lib_name_path("vhpi", "activehdl") + ":cocotbvpi_entry_point"
+                self.env["GPI_EXTRA"] = cocotb_config.lib_name_path("vhpi", "activehdl") + ":cocotbvpi_entry_point"
 
         if self.waves:
             do_script += "trace -recursive /*;"

tests/test_cocotb_examples.py

@@ -2,9 +2,15 @@
 import cocotb
 import pytest
 
+from cocotb_test.compat import cocotb_2x_or_newer
 from cocotb_test.simulator import run
 
-example_dir = os.path.join(os.path.dirname(os.path.dirname(cocotb.__file__)), "examples")
+if cocotb_2x_or_newer:
+    cocotb_repo_root = os.path.dirname(os.path.dirname(os.path.dirname(cocotb.__file__)))
+else:
+    cocotb_repo_root = os.path.dirname(os.path.dirname(cocotb.__file__))
+
+example_dir = os.path.join(cocotb_repo_root, "examples")
 
 if os.path.isdir(example_dir) == False:
     raise IOError("Cocotb example directory not found. Please clone with git and install with `pip -e`")

tests/test_cocotb_tests.py

@@ -3,9 +3,15 @@
 import pytest
 import sys
 
+from cocotb_test.compat import cocotb_2x_or_newer
 from cocotb_test.simulator import run
 
-tests_dir = os.path.join(os.path.dirname(os.path.dirname(cocotb.__file__)), "tests")
+if cocotb_2x_or_newer:
+    cocotb_repo_root = os.path.dirname(os.path.dirname(os.path.dirname(cocotb.__file__)))
+else:
+    cocotb_repo_root = os.path.dirname(os.path.dirname(cocotb.__file__))
+
+tests_dir = os.path.join(cocotb_repo_root, "tests")
 
 if os.path.isdir(tests_dir) == False:
     raise IOError(

tests/test_dff_custom_sim.py

@@ -3,6 +3,7 @@
 import pytest
 import os
 import cocotb
+from cocotb_test.compat import cocotb_config
 
 hdl_dir = os.path.dirname(__file__)
 
@@ -13,7 +14,7 @@ def __init__(self, logfile, *argv, **kwargs):
 
     def run_command(self):
         return (
-            ["vvp", "-v", "-l", self.logfile, "-M", self.lib_dir, "-m", cocotb.config.lib_name("vpi", "icarus")]
+            ["vvp", "-v", "-l", self.logfile, "-M", self.lib_dir, "-m", cocotb_config.lib_name("vpi", "icarus")]
             + self.simulation_args
             + [self.sim_file]
             + self.plus_args

tests/test_long_log.py

@@ -9,9 +9,9 @@
 
 
 @cocotb.test()
-def run_test_long_log(dut):
+async def run_test_long_log(dut):
 
-    yield Timer(1)
+    await Timer(1)
 
     dut._log.info("BEFORE")
     dut._log.info("LONGLOG" * 100000)

tests/test_multitop.py

@@ -1,11 +1,9 @@
-from cocotb.regression import TestFactory
 from cocotb_test.simulator import run
 import pytest
 import os
 
 import cocotb
 from cocotb.triggers import Timer, ReadOnly
-from cocotb.result import TestFailure
 
 tests_dir = os.path.dirname(__file__)
 
@@ -26,15 +24,14 @@ def test_dff_verilog():
 @cocotb.test()
 async def glbl(dut):
     await ReadOnly()
-    if dut.rst.value == 0:
-        raise TestFailure()
+    assert dut.rst.value != 0
+
     # BEWARE: Timer(10) is equal to Timer(10, 'step') which is ten simulator *precision* steps.
     # Only the same as Verilog delay '#10' (ten *time units*) when timescale directive sets
     # the time unit same as precision ie. with timescale="1ns/1ns" or "1ps/1ps"
     await Timer(10)
     await ReadOnly()
-    if dut.rst.value == 1:
-        raise TestFailure()
+    assert dut.rst.value != 1
 
 
 if __name__ == "__main__":

tests/test_parameters.py

@@ -9,9 +9,9 @@
 
 
 @cocotb.test()
-def run_test_paramters(dut):
+async def run_test_parameters(dut):
 
-    yield Timer(1)
+    await Timer(1)
 
     WIDTH_IN = int(os.environ.get("WIDTH_IN", "8"))
     WIDTH_OUT = int(os.environ.get("WIDTH_OUT", "8"))

tests/test_plus_args.py

@@ -8,9 +8,9 @@
 hdl_dir = os.path.dirname(__file__)
 
 @cocotb.test(skip=False)
-def run_test(dut):
+async def run_test(dut):
 
-    yield Timer(1)
+    await Timer(1)
 
     user_mode = int(dut.user_mode)