Merge pull request #1051 from ved-rivos/double_trap

Update resume from Debug Mode behavior with Smdbltrp
riscv · Jul 10, 2024 · d0c692a · d0c692a
2 parents e7d31f8 + a5c8c29
commit d0c692a
Show file tree

Hide file tree

Showing 2 changed files with 6 additions and 1 deletion.
diff --git a/Sdext.adoc b/Sdext.adoc
@@ -192,6 +192,11 @@ When a hart resumes:
 . The current privilege mode and virtualization mode are changed to that
 specified by {dcsr-prv} and {dcsr-v}.
 . If the new privilege mode is less privileged than M-mode, `MPRV` in `mstatus` is cleared.
+. If the Smdbltrp extension is implemented and the new privilege mode is not M,
+  then the `MDT` bit is set to 0.
+. If the Ssdbltrp extension is implemented and the new privilege mode is U, VS,
+  or VU, then `sstatus.SDT` is set to 0. Additionally, if it is VU, then
+  `vsstatus.SDT` is also set to 0.
 . The hart is no longer in debug mode.
 
 [[debreg]]

diff --git a/xml/core_registers.xml b/xml/core_registers.xml
@@ -84,7 +84,7 @@ same project unless stated otherwise.
             for use by other RISC-V extensions.
         </field>
         <field name="0" bits="23:20" access="R" reset="0" />
-        <field name="cetrig" bits="19" access="R/W" reset="0">
+        <field name="cetrig" bits="19" access="WARL" reset="0">
             This bit is part of ((Smdbltrp)) and only exists when that extension
             is implemented.