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Recommend debug ROM is not cached. #866

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Sep 11, 2023
Merged

Recommend debug ROM is not cached. #866

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2 changes: 2 additions & 0 deletions implementations.tex
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Expand Up @@ -30,6 +30,8 @@ \section{Execution Based} \label{execution_based}
to the selected harts. This interrupt causes each
hart to enter Debug Mode and jump to a defined
memory region that is serviced by the DM and is only accessible to the harts in Debug Mode.
Accesses to this memory should be uncached to avoid side effects from
debugging operations.
When taking this jump, \Rpc is saved to \RcsrDpc and \FcsrDcsrCause is updated
in \RcsrDcsr. This jump is similar to a trap but it is not architecturally
considered a trap, so for instance doesn't count as a trap for trigger behavior.
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